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| author | Wade Fife <wade.fife@ettus.com> | 2020-08-26 13:50:06 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-08-28 15:07:38 -0500 |
| commit | d352f5a9c3bd3791f0320be1e615146fe7459453 (patch) | |
| tree | 0ed06dbc230edb60f50542686c93d04001abcdaa /.clang-format | |
| parent | 7c849afec4dad605ff6f32f7319933f99a4cd1ce (diff) | |
| download | uhd-d352f5a9c3bd3791f0320be1e615146fe7459453.tar.gz uhd-d352f5a9c3bd3791f0320be1e615146fe7459453.tar.bz2 uhd-d352f5a9c3bd3791f0320be1e615146fe7459453.zip | |
fpga: e320: Update AXI interconnect address range
This change allows the entire 2 GiB address space to be accessed on
each memory port.
Diffstat (limited to '.clang-format')
0 files changed, 0 insertions, 0 deletions