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author | Martin Braun <martin.braun@ettus.com> | 2021-09-16 13:33:23 +0200 |
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committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-09-17 13:29:01 -0700 |
commit | 6c8f24a9ca136c78fd73e94e937b3325a26a1fab (patch) | |
tree | ade34172b63790bc1d6f98078b7259c38ff19c46 /.ci/docker | |
parent | 652873b664393120b284e3303f82f80c7a1f4f9a (diff) | |
download | uhd-6c8f24a9ca136c78fd73e94e937b3325a26a1fab.tar.gz uhd-6c8f24a9ca136c78fd73e94e937b3325a26a1fab.tar.bz2 uhd-6c8f24a9ca136c78fd73e94e937b3325a26a1fab.zip |
ad9361: Modify set-tx-gain procedure to update gain in one go
The previous behaviour of UHD for setting gain was:
1. Set "Mask Clr Atten Update". This will avoid "Immediately Update TPC
Atten" to be cleared.
2. Then, assert "Immediately Update TPC Atten".
3. Poke the LSBs of the attenuation value.
4. Poke the MSB of the attenuation value.
This order of operations has the downside of causing large Tx power
spikes when setting the attenuation, because you need both registers to
properly set the attenuation, but we are updating the gain immediately,
even between the two attenuation register's update.
Moreover, the upstream Linux driver for AD9361 by ADI also does not
do this. We therefore change the procedure to match the kernel driver
behaviour, which is:
0. [During initialization: Clear "Mask Clr Atten Update"
1. Poke the attenuation registers
2. Then, assert "Immediately Update TPC Atten".
This avoids Tx power spikes. It also reduces the Tx-gain procedure to
3 pokes instead of 4.
Diffstat (limited to '.ci/docker')
0 files changed, 0 insertions, 0 deletions