diff options
author | Matthias P. Braendli <matthias.braendli@mpb.li> | 2019-11-26 17:29:16 +0100 |
---|---|---|
committer | Matthias P. Braendli <matthias.braendli@mpb.li> | 2019-11-26 17:29:16 +0100 |
commit | 049cb8689584aa860daa3512e864b0190605a0db (patch) | |
tree | 92379940c62905c301c0bdaf4d1b49c76f3f0516 /kicad/renard.pro | |
parent | 07124d10e993476c27772e2997fab7de16ffe807 (diff) | |
download | renard_hb9hi-049cb8689584aa860daa3512e864b0190605a0db.tar.gz renard_hb9hi-049cb8689584aa860daa3512e864b0190605a0db.tar.bz2 renard_hb9hi-049cb8689584aa860daa3512e864b0190605a0db.zip |
Update with new version from HB9ICJ
Diffstat (limited to 'kicad/renard.pro')
-rw-r--r-- | kicad/renard.pro | 281 |
1 files changed, 227 insertions, 54 deletions
diff --git a/kicad/renard.pro b/kicad/renard.pro index 532727e..ff5b419 100644 --- a/kicad/renard.pro +++ b/kicad/renard.pro @@ -1,65 +1,238 @@ -update=Thu 13 Jul 2017 19:15:03 CEST +update=Mon 10 Jun 2019 14:54:03 CEST version=1 last_client=kicad -[cvpcb] -version=1 -NetIExt=net -[cvpcb/libraries] -EquName1=devcms [general] version=1 -[pcbnew] +RootSch= +BoardNm= +[cvpcb] version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=" 0.600000" -PadDrillOvalY=" 0.600000" -PadSizeH=" 1.500000" -PadSizeV=" 1.500000" -PcbTextSizeV=" 1.500000" -PcbTextSizeH=" 1.500000" -PcbTextThickness=" 0.300000" -ModuleTextSizeV=" 1.000000" -ModuleTextSizeH=" 1.000000" -ModuleTextSizeThickness=" 0.150000" -SolderMaskClearance=" 0.000000" -SolderMaskMinWidth=" 0.000000" -DrawSegmentWidth=" 0.200000" -BoardOutlineThickness=" 0.100000" -ModuleOutlineThickness=" 0.150000" -[pcbnew/libraries] -LibDir= -LibName1=sockets -LibName2=connect -LibName3=discret -LibName4=pin_array -LibName5=divers -LibName6=smd_capacitors -LibName7=smd_resistors -LibName8=smd_crystal&oscillator -LibName9=smd_dil -LibName10=smd_transistors -LibName11=libcms -LibName12=display -LibName13=led -LibName14=dip_sockets -LibName15=pga_sockets -LibName16=valves -LibName17=40xx -LibName18=attiny24_44_84 -LibName19=crystal +NetIExt=net [eeschema] version=1 LibDir= [eeschema/libraries] -LibName1=renard -[schematic_editor] +[pcbnew] version=1 PageLayoutDescrFile= -PlotDirectoryName= -SubpartIdSeparator=0 -SubpartFirstId=65 -NetFmtName= -SpiceForceRefPrefix=0 -SpiceUseNetNumbers=0 -LabSize=60 +LastNetListRead=renard.net +CopperLayerCount=2 +BoardThickness=1.6 +AllowMicroVias=0 +AllowBlindVias=0 +RequireCourtyardDefinitions=0 +ProhibitOverlappingCourtyards=1 +MinTrackWidth=0.25 +MinViaDiameter=0.4 +MinViaDrill=0.3 +MinMicroViaDiameter=0.2 +MinMicroViaDrill=0.09999999999999999 +MinHoleToHole=0.25 +TrackWidth1=0.25 +ViaDiameter1=0.8 +ViaDrill1=0.4 +dPairWidth1=0.2 +dPairGap1=0.25 +dPairViaGap1=0.25 +SilkLineWidth=0.12 +SilkTextSizeV=1 +SilkTextSizeH=1 +SilkTextSizeThickness=0.15 +SilkTextItalic=0 +SilkTextUpright=1 +CopperLineWidth=0.2 +CopperTextSizeV=1.5 +CopperTextSizeH=1.5 +CopperTextThickness=0.3 +CopperTextItalic=0 +CopperTextUpright=1 +EdgeCutLineWidth=0.05 +CourtyardLineWidth=0.05 +OthersLineWidth=0.15 +OthersTextSizeV=1 +OthersTextSizeH=1 +OthersTextSizeThickness=0.15 +OthersTextItalic=0 +OthersTextUpright=1 +SolderMaskClearance=0.051 +SolderMaskMinWidth=0.25 +SolderPasteClearance=0 +SolderPasteRatio=0 +[pcbnew/Layer.F.Cu] +Name=F.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.In1.Cu] +Name=In1.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In2.Cu] +Name=In2.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In3.Cu] +Name=In3.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In4.Cu] +Name=In4.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In5.Cu] +Name=In5.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In6.Cu] +Name=In6.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In7.Cu] +Name=In7.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In8.Cu] +Name=In8.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In9.Cu] +Name=In9.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In10.Cu] +Name=In10.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In11.Cu] +Name=In11.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In12.Cu] +Name=In12.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In13.Cu] +Name=In13.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In14.Cu] +Name=In14.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In15.Cu] +Name=In15.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In16.Cu] +Name=In16.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In17.Cu] +Name=In17.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In18.Cu] +Name=In18.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In19.Cu] +Name=In19.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In20.Cu] +Name=In20.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In21.Cu] +Name=In21.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In22.Cu] +Name=In22.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In23.Cu] +Name=In23.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In24.Cu] +Name=In24.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In25.Cu] +Name=In25.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In26.Cu] +Name=In26.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In27.Cu] +Name=In27.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In28.Cu] +Name=In28.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In29.Cu] +Name=In29.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In30.Cu] +Name=In30.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.B.Cu] +Name=B.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.B.Adhes] +Enabled=1 +[pcbnew/Layer.F.Adhes] +Enabled=1 +[pcbnew/Layer.B.Paste] +Enabled=1 +[pcbnew/Layer.F.Paste] +Enabled=1 +[pcbnew/Layer.B.SilkS] +Enabled=1 +[pcbnew/Layer.F.SilkS] +Enabled=1 +[pcbnew/Layer.B.Mask] +Enabled=1 +[pcbnew/Layer.F.Mask] +Enabled=1 +[pcbnew/Layer.Dwgs.User] +Enabled=1 +[pcbnew/Layer.Cmts.User] +Enabled=1 +[pcbnew/Layer.Eco1.User] +Enabled=1 +[pcbnew/Layer.Eco2.User] +Enabled=1 +[pcbnew/Layer.Edge.Cuts] +Enabled=1 +[pcbnew/Layer.Margin] +Enabled=1 +[pcbnew/Layer.B.CrtYd] +Enabled=1 +[pcbnew/Layer.F.CrtYd] +Enabled=1 +[pcbnew/Layer.B.Fab] +Enabled=1 +[pcbnew/Layer.F.Fab] +Enabled=1 +[pcbnew/Layer.Rescue] +Enabled=0 +[pcbnew/Netclasses] +[pcbnew/Netclasses/Default] +Name=Default +Clearance=0.2 +TrackWidth=0.25 +ViaDiameter=0.8 +ViaDrill=0.4 +uViaDiameter=0.3 +uViaDrill=0.1 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 |