diff options
| -rw-r--r-- | .gitignore | 2 | ||||
| -rw-r--r-- | Cargo.lock | 154 | ||||
| -rw-r--r-- | Cargo.toml | 13 | ||||
| -rw-r--r-- | LICENSE | 340 | ||||
| -rw-r--r-- | README.md | 28 | ||||
| -rw-r--r-- | build.rs | 19 | ||||
| -rw-r--r-- | src/kiss.rs | 183 | ||||
| -rw-r--r-- | src/kissattach.c | 137 | ||||
| -rw-r--r-- | src/lib.rs | 7 | ||||
| -rw-r--r-- | src/main.rs | 111 | ||||
| -rw-r--r-- | src/rfm95.rs | 656 |
11 files changed, 1650 insertions, 0 deletions
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"3d68f2cae3c7d39f54ce8a858cc31ffb01974744ee65e5b4999b6037cd691e3f" +"checksum void 1.0.2 (registry+https://github.com/rust-lang/crates.io-index)" = "6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d" +"checksum winapi 0.2.8 (registry+https://github.com/rust-lang/crates.io-index)" = "167dc9d6949a9b857f3451275e911c3f44255842c1f7a76f33c55103a909087a" diff --git a/Cargo.toml b/Cargo.toml new file mode 100644 index 0000000..5827d1c --- /dev/null +++ b/Cargo.toml @@ -0,0 +1,13 @@ +[package] +name = "raspi-rfm95-kiss" +version = "0.1.0" +authors = ["Matthias P. Braendli <matthias.braendli@mpb.li>"] + +[build-dependencies] +cc = "1.0" + +[dependencies] +libc = "0.2" +#wiringpi = "0.2" +spidev = "0.3.0" +sysfs_gpio = "0.5" @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. 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See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + <signature of Ty Coon>, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/README.md b/README.md new file mode 100644 index 0000000..bfbfcd5 --- /dev/null +++ b/README.md @@ -0,0 +1,28 @@ +raspi-rfm95-kiss +================ + +Use an RFM95 LoRa module connected to spidev0.0 as an AX.25 interface. The whole chain this code implements is: + +AX.25 kernel interface - KISS protocol over a PTY pair - KISS protocol implementation - RFM95 driver - SPI + +TODO +==== + +* [ ] KISS protocol implementation +* [ ] RFM95 send +* [ ] RFM95 recv in polling mode +* [ ] RFM95 recv in GPIO interrupt mode + + +License +------- + +Parts of this code are taken from the ax25-tools, which are GPL-2.0. Other parts are MIT or Apache 2.0 licensed. + +New code is Copyright 2018 Matthias P. Braendli, GPL-2.0-only + + +Misc remarks +------------ + +1. (Not needed) To build with wiringpi in dev mode: `cargo build --features wiringpi/development` diff --git a/build.rs b/build.rs new file mode 100644 index 0000000..5e14209 --- /dev/null +++ b/build.rs @@ -0,0 +1,19 @@ +// Copyright 2018 Matthias P. Braendli +// SPDX-License-Identifier: GPL-2.0-only + +extern crate cc; + +fn main() { + cc::Build::new() + .file("src/kissattach.c") + .compile("kissattach"); + + println!("cargo:rustc-link-lib=ax25"); + + /* + .file("bar.c") + .define("FOO", Some("bar")) + .include("src") + .compile("foo"); + */ +} diff --git a/src/kiss.rs b/src/kiss.rs new file mode 100644 index 0000000..397922d --- /dev/null +++ b/src/kiss.rs @@ -0,0 +1,183 @@ +// Taken from ax25-rs, which is +// SPDX-License-Identifier: Apache-2.0 +use std::io; +use std::io::prelude::*; +use std::io::{Read, Write}; + +const FEND: u8 = 0xC0; +const FESC: u8 = 0xDB; +const TFEND: u8 = 0xDC; +const TFESC: u8 = 0xDD; + +pub struct KissDecoder<'a> { + stream: &'a Read, + buffer: Vec<u8> +} + +impl<'a> KissDecoder<'a> { + pub fn new<T>(stream: &T) -> io::Result<KissDecoder> + where T: Read + { + Ok(KissDecoder { + stream: stream, + buffer: Vec::new() + }) + } + + pub fn receive_frame(&mut self) -> io::Result<Vec<u8>> { + loop { + if let Some(frame) = make_frame_from_buffer(&mut self.buffer) { + return Ok(frame); + } + let mut buf = vec![0u8; 1024]; + let n_bytes = self.stream.read(&mut buf)?; + self.buffer.extend(buf.iter().take(n_bytes)); + } + } +} + +/* +pub struct KissEncoder { + stream: Write, + buffer: Vec<u8> +} + +impl KissEncoder { + pub fn new(stream: Write) -> io::Result<KissEncoder> { + Ok(KissEncoder { + stream: stream, + buffer: Vec::new() + }) + } + + pub fn send_frame(&mut self, frame: &[u8]) -> io::Result<()> { + // 0x00 is the KISS command byte, which is two nybbles + // port = 0 + // command = 0 (all following bytes are a data frame to transmit) + self.stream.write(&[FEND, 0x00])?; + self.stream.write(frame)?; + self.stream.write(&[FEND])?; + self.stream.flush()?; + Ok(()) + } +} + +fn make_frame_from_buffer(buffer: &mut Vec<u8>) -> Option<Vec<u8>> { + let mut possible_frame = Vec::new(); + + enum Scan { + LookingForStartMarker, + Data, + Escaped + } + let mut state = Scan::LookingForStartMarker; + let mut final_idx = 0; + + // Check for possible frame read-only until we know we have a complete frame + // If we take one out, clear out buffer up to the final index + for (idx, &c) in buffer.iter().enumerate() { + match state { + Scan::LookingForStartMarker => { + if c == FEND { + state = Scan::Data; + } + }, + Scan::Data => { + if c == FEND { + if !possible_frame.is_empty() { + // Successfully read a non-zero-length frame + final_idx = idx; + break; + } + } else if c == FESC { + state = Scan::Escaped; + } else { + possible_frame.push(c); + } + }, + Scan::Escaped => { + if c == TFEND { + possible_frame.push(FEND); + } else if c == TFESC { + possible_frame.push(FESC); + } else if c == FEND { + if !possible_frame.is_empty() { + // Successfully read a non-zero-length frame + final_idx = idx; + break; + } + } + state = Scan::Data; + } + } + } + + match final_idx { + 0 => None, + n => { + // Draining up to "n" will leave the final FEND in place + // This way we can use it as the start marker for the next frame + buffer.drain(0..n); + Some(possible_frame) + } + } +} + +#[test] +fn test_normal_frame() { + let mut rx = vec![FEND, 0x01, 0x02, FEND]; + assert_eq!(make_frame_from_buffer(&mut rx), Some(vec![0x01, 0x02])); + assert_eq!(rx, vec![FEND]); +} + +#[test] +fn test_trailing_data() { + let mut rx = vec![FEND, 0x01, 0x02, FEND, 0x03, 0x04]; + assert_eq!(make_frame_from_buffer(&mut rx), Some(vec![0x01, 0x02])); + assert_eq!(rx, vec![FEND, 0x03, 0x04]); +} + +#[test] +fn test_leading_data() { + let mut rx = vec![0x03, 0x04, FEND, 0x01, 0x02, FEND]; + assert_eq!(make_frame_from_buffer(&mut rx), Some(vec![0x01, 0x02])); + assert_eq!(rx, vec![FEND]); +} + +#[test] +fn test_consecutive_marker() { + let mut rx = vec![FEND, FEND, FEND, 0x01, 0x02, FEND]; + assert_eq!(make_frame_from_buffer(&mut rx), Some(vec![0x01, 0x02])); + assert_eq!(rx, vec![FEND]); +} + +#[test] +fn test_escapes() { + let mut rx = vec![FEND, 0x01, FESC, TFESC, 0x02, FESC, TFEND, 0x03, FEND]; + assert_eq!(make_frame_from_buffer(&mut rx), Some(vec![0x01, FESC, 0x02, FEND, 0x03])); + assert_eq!(rx, vec![FEND]); +} + +#[test] +fn test_incorrect_escape_skipped() { + let mut rx = vec![FEND, 0x01, FESC, 0x04, TFESC /* passes normally without leading FESC */, 0x02, FEND]; + assert_eq!(make_frame_from_buffer(&mut rx), Some(vec![0x01, TFESC, 0x02])); + assert_eq!(rx, vec![FEND]); +} + +#[test] +fn test_two_frames_single_fend() { + let mut rx = vec![FEND, 0x01, 0x02, FEND, 0x03, 0x04, FEND]; + assert_eq!(make_frame_from_buffer(&mut rx), Some(vec![0x01, 0x02])); + assert_eq!(make_frame_from_buffer(&mut rx), Some(vec![0x03, 0x04])); + assert_eq!(rx, vec![FEND]); +} + +#[test] +fn test_two_frames_double_fend() { + let mut rx = vec![FEND, 0x01, 0x02, FEND, FEND, 0x03, 0x04, FEND]; + assert_eq!(make_frame_from_buffer(&mut rx), Some(vec![0x01, 0x02])); + assert_eq!(make_frame_from_buffer(&mut rx), Some(vec![0x03, 0x04])); + assert_eq!(rx, vec![FEND]); +} +*/ diff --git a/src/kissattach.c b/src/kissattach.c new file mode 100644 index 0000000..74d4efb --- /dev/null +++ b/src/kissattach.c @@ -0,0 +1,137 @@ +// Taken from ax25-tools 0.0.10-rc4 kissattach.c +// SPDX-License-Identifier: GPL-2.0-only +#include <stdio.h> +#define __USE_XOPEN +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <termios.h> +#include <fcntl.h> +#include <signal.h> +#include <ctype.h> +#include <netdb.h> +#include <syslog.h> +#include <errno.h> + +#include <sys/types.h> +#include <sys/stat.h> +#include <sys/socket.h> +#include <sys/ioctl.h> + +#include <net/if.h> +#include <netax25/ax25.h> +#include <netrose/rose.h> + +#include <netax25/daemon.h> +#include <netax25/axlib.h> +#include <netax25/ttyutils.h> + + +static int setifcall(int fd, char *name) +{ + char call[7]; + + if (ax25_aton_entry(name, call) == -1) + return FALSE; + + if (ioctl(fd, SIOCSIFHWADDR, call) != 0) { + close(fd); + perror("SIOCSIFHWADDR"); + return FALSE; + } + + return TRUE; +} + + +static int startiface(char *dev, int mtu, int allow_broadcast) +{ + struct ifreq ifr; + int fd; + + if ((fd = socket(AF_INET, SOCK_DGRAM, 0)) < 0) { + perror("socket"); + return FALSE; + } + + strcpy(ifr.ifr_name, dev); + + ifr.ifr_mtu = mtu; + + if (ioctl(fd, SIOCSIFMTU, &ifr) < 0) { + perror("SIOCSIFMTU"); + return FALSE; + } + + if (ioctl(fd, SIOCGIFFLAGS, &ifr) < 0) { + perror("SIOCGIFFLAGS"); + return FALSE; + } + + ifr.ifr_flags &= IFF_NOARP; + ifr.ifr_flags |= IFF_UP; + ifr.ifr_flags |= IFF_RUNNING; + if (allow_broadcast) + ifr.ifr_flags |= IFF_BROADCAST; /* samba broadcasts are a pain.. */ + else + ifr.ifr_flags &= ~(IFF_BROADCAST); /* samba broadcasts are a pain.. */ + + if (ioctl(fd, SIOCSIFFLAGS, &ifr) < 0) { + perror("SIOCSIFFLAGS"); + return FALSE; + } + + close(fd); + + return TRUE; +} + +int32_t kissattach( + char *callsign, + int32_t speed, + int32_t mtu, + char *kttyname, + int32_t allow_broadcast) +{ + int fd; + int disc = N_AX25; + char dev[64]; + + if ((fd = open(kttyname, O_RDONLY | O_NONBLOCK)) == -1) { + perror("open"); + return 0; + } + + if (speed != 0 && !tty_speed(fd, speed)) + return 0; + + if (ioctl(fd, TIOCSETD, &disc) == -1) { + //Error setting line discipline + perror("TIOCSETD"); + fprintf(stderr, "Are you sure you have enabled %s support in the kernel\n", + disc == N_AX25 ? "MKISS" : "6PACK"); + fprintf(stderr, "or, if you made it a module, that the module is loaded?\n"); + return 0; + } + + if (ioctl(fd, SIOCGIFNAME, dev) == -1) { + perror("SIOCGIFNAME"); + return 0; + } + + if (!setifcall(fd, callsign)) + return 0; + + /* Now set the encapsulation */ + int v = 4; + if (ioctl(fd, SIOCSIFENCAP, &v) == -1) { + perror("SIOCSIFENCAP"); + return 0; + } + + /* ax25 ifaces should not really need to have an IP address assigned to */ + if (!startiface(dev, mtu, allow_broadcast)) + return 0; + + return 1; +} diff --git a/src/lib.rs b/src/lib.rs new file mode 100644 index 0000000..15e4720 --- /dev/null +++ b/src/lib.rs @@ -0,0 +1,7 @@ +// Copyright 2018 Matthias P. Braendli +// SPDX-License-Identifier: GPL-2.0-only +extern crate spidev; +extern crate sysfs_gpio; + +pub mod rfm95; +pub mod kiss; diff --git a/src/main.rs b/src/main.rs new file mode 100644 index 0000000..9073975 --- /dev/null +++ b/src/main.rs @@ -0,0 +1,111 @@ +// Copyright 2018 Matthias P. Braendli +// SPDX-License-Identifier: GPL-2.0-only +extern crate libc; + +extern crate raspi_rfm95_kiss; +use raspi_rfm95_kiss::rfm95::{RF95, Bandwidth, CodingRate, SpreadingFactor}; +use std::fs::{OpenOptions, File}; +use std::ffi::{CStr, CString}; +use std::os::unix::io::AsRawFd; + +const MAX_MTU: usize = 251; + +extern { + fn kissattach( + callsign: * const libc::c_char, + speed: libc::int32_t, + mtu: libc::int32_t, + kttyname: * const libc::c_char, + allow_broadcast: libc::int32_t) -> libc::int32_t; +} + +fn create_pts_pair() -> std::io::Result<File> { + let master_file = OpenOptions::new() + .read(true) + .write(true) + .open("/dev/ptmx")?; + + unsafe { + let master_fd = master_file.as_raw_fd(); + if libc::grantpt(master_fd) == -1 { + return Err(std::io::Error::last_os_error()); + } + if libc::unlockpt(master_fd) == -1 { + return Err(std::io::Error::last_os_error()); + } + } + + Ok(master_file) +} + +fn main() { + println!("Creating PTY pair"); + + let master_file = match create_pts_pair() { + Ok(fd) => fd, + Err(e) => panic!("create_pts_pair failed: {}", e) + }; + + let slavename; + unsafe { + slavename = libc::ptsname(master_file.as_raw_fd()); + } + + if slavename.is_null() { + panic!("Cannot get PTS slave name"); + } + unsafe { + let slice = CStr::from_ptr(slavename); + println!("PTS slave: {:?}", slice); + } + + match RF95::new(Bandwidth::Bw250, CodingRate::Cr8, SpreadingFactor::Sf10) { + Ok(mut radio) => { + radio.reset().expect("radio reset"); + + if let Ok(ver) = radio.get_version() { + println!("Device version: {:02x}", ver); + } + else { + println!("Cannot read device version"); + } + }, + Err(e) => panic!("Cannot create lora radio object, {}", e) + }; + + let callsign = CString::new("HB9EGM-1").expect("Failed to convert callsign to CString"); + let speed : i32 = 9600; + let mtu : i32 = 251; + let allow_broadcast : i32 = 1; + + let success = unsafe { + kissattach( + callsign.as_ptr(), + speed, + mtu, + slavename, + allow_broadcast) + }; + + if success == 0 { + panic!("kissattach failed"); + } + + let todo = "Read/Write from/to TTY and RFM95"; + + /* + let master_tty = Box::new(master_file); + + let writer = thread::spawn(|| { + loop { + let mut buffer = [0; MAX_MTU]; + match *master_tty.read(&mut buffer[..]) { + Ok(n) => radio.write_buffer(buffer), + Err(e) => panic!("TTY Read error {}", e); + } + } + }); + + writer.join().unwrap(); + */ +} diff --git a/src/rfm95.rs b/src/rfm95.rs new file mode 100644 index 0000000..f4da72b --- /dev/null +++ b/src/rfm95.rs @@ -0,0 +1,656 @@ +// Taken from rfm95_rust_pi, which is +// SPDX-License-Identifier: MIT +use std; +use sysfs_gpio; +use sysfs_gpio::{Direction, Edge, Pin}; +use spidev::{Spidev, SpidevOptions, SPI_MODE_0}; +use std::io; +use std::thread; +use std::time::Duration; +use std::io::{Read, Write, ErrorKind}; +use std::sync::mpsc::{Receiver}; +use std::sync::mpsc; +use std::sync::atomic::{AtomicBool, Ordering}; + +const RST_BCM_PIN : u64 = 17; +const DIO_BCM_PIN : u64 = 4; +const CS_BCM_PIN : u64 = 25; + +#[derive(Copy, Clone)] +pub enum LoraRegister { + RegFifo = 0x00, + RegOpMode = 0x01, + // reserved : 0x02 - 0x05 + RegFrfMsb = 0x06, + RegFrfMid = 0x07, + RegFrfLsb = 0x08, + RegPaConfig = 0x09, + RegPaRamp = 0x0A, + RegOcp = 0x0B, + RegLna = 0x0C, + RegFifoAddrPtr = 0x0D, + RegFifoTxBaseAddr = 0x0E, + RegFifoRxBaseAddr = 0x0F, + RegFifoRxCurrentAddr = 0x10, + RegIrqFlagsMask = 0x11, + RegIrqFlags = 0x12, + RegRxNbBytes = 0x13, + RegRxHeaderCntValueMsb = 0x14, + RegRxHeaderCntValueLsb = 0x15, + RegRxPacketCntValueMsb = 0x16, + RegRxPacketCntValueLsb = 0x17, + RegModemStat = 0x18, + RegPktSnrValue = 0x19, + RegPktRssiValue = 0x1A, + RegRssiValue = 0x1B, + RegHopChannel = 0x1C, + RegModemConfig1 = 0x1D, + RegModemConfig2 = 0x1E, + RegSymbTimeoutLsb = 0x1F, + RegPreambleMsb = 0x20, + RegPreambleLsb = 0x21, + RegPayloadLength = 0x22, + RegMaxPayloadLength = 0x23, + RegHopPeriod = 0x24, + RegFifoRxByteAddr = 0x25, + RegModemConfig3 = 0x26, + // reserved : 0x27-0x3F + RegDioMapping1 = 0x40, + RegDioMapping2 = 0x41, + RegVersion = 0x42, + // unused 0x44 + RegTcxo = 0x4B, + RegPaDac = 0x4D, + RegFormerTemp = 0x5B, + RegAgcRef = 0x61, + RegAgcThresh1 = 0x62, + RegAgcThresh2 = 0x63, + RegAgcThresh3 = 0x64, +} + +impl LoraRegister { + pub fn as_u8(&self) -> u8 { + *self as u8 + } +} + +#[derive(Copy, Clone)] +pub enum FskOokRegister { + RegFifo = 0x00, + RegOpMode = 0x01, + RegBitRateMsb = 0x02, + RegBitRateLsb = 0x03, + RegFdevMsb = 0x04, + RegFdevLsb = 0x05, + RegFrfMsb = 0x06, + RegFrfMid = 0x07, + RegFrfLsb = 0x08, + RegPaConfig = 0x09, + RegPaRamp = 0x0A, + RegOcp = 0x0B, + RegLna = 0x0C, + RegRxConfig = 0x0D, + RegRssiConfig = 0x0E, + RegRssiCollision = 0x0F, + RegRssiThresh = 0x10, + RegRssiValue = 0x11, + RegRxBw = 0x12, + RegAfcBw = 0x13, + RegOokPeak = 0x14, + RegOokFix = 0x15, + RegOokAvg = 0x16, + RegAfcFei = 0x1A, + RegAfcMsb = 0x1B, + RegAfcLsb = 0x1C, + RegFeiMsb = 0x1D, + RegFeiLsb = 0x1E, + RegPreambleDetect = 0x1F, + RegRxTimeout1 = 0x20, + RegRxTimeout2 = 0x21, + RegRxTimeout3 = 0x22, + RegRxDelay = 0x23, + RegOsc = 0x24, + RegPreambleMsb = 0x25, + RegPreambleLsb = 0x26, + RegSyncConfig = 0x27, + RegSyncValue1 = 0x28, + RegSyncValue2 = 0x29, + RegSyncValue3 = 0x2A, + RegSyncValue4 = 0x2B, + RegSyncValue5 = 0x2C, + RegSyncValue6 = 0x2D, + RegSyncValue7 = 0x2E, + RegSyncValue8 = 0x2F, + RegPacketconfig1 = 0x30, + RegPacketConfig2 = 0x31, + RegPayloadLength = 0x32, + RegNodeAdrs = 0x33, + RegBroadcastAdrs = 0x34, + RegFifoThresh = 0x35, + RegSeqConfig1 = 0x36, + RegSeqConfig2 = 0x37, + RegTimerResol = 0x38, + RegTimer1Coef = 0x39, + RegTimer2Coef = 0x3A, + RegImageCal = 0x3B, + RegTemp = 0x3C, + RegLowBat = 0x3D, + RegIrqFlags1 = 0x3E, + RegIrqFlags2 = 0x3F, + RegDioMapping1 = 0x40, + RegDioMapping2 = 0x41, + RegVersion = 0x42, + RegPllHop = 0x44, + RegTxco = 0x4B, + RegPaDac = 0x4D, + RegFormerTemp = 0x5B, + RegBitRateFrac = 0x5D, + RegAgcRef = 0x61, + RegAgcThresh1 = 0x62, + RegAgcThresh2 = 0x63, + RegAgcThresh3 = 0x64, +} + +impl FskOokRegister { + pub fn as_u8(&self) -> u8 { + *self as u8 + } +} + +#[derive(Copy, Clone)] +pub enum Channel { + Ch10 = 0xD84CCC, + Ch11 = 0xD86000, + Ch12 = 0xD87333, + Ch13 = 0xD88666, + Ch14 = 0xD89999, + Ch15 = 0xD8ACCC, + Ch16 = 0xD8C000, + Ch17 = 0xD90000, +} + +impl Channel { + pub fn msb(&self) -> u8 { + let chan_as_u8 = *self as u32; + ((chan_as_u8 >> 16) & 0x000000FF) as u8 + } + + pub fn mid(&self) -> u8 { + let chan_as_u8 = *self as u32; + ((chan_as_u8 >> 8) & 0x000000FF) as u8 + } + + pub fn lsb(&self) -> u8 { + let chan_as_u8 = *self as u32; + (chan_as_u8 & 0x000000FF) as u8 + } +} + +#[derive(Copy, Clone)] +pub enum Bandwidth { + Bw125 = 0x07, + Bw250 = 0x08, + Bw500 = 0x09, +} + +impl Bandwidth { + pub fn as_u8(&self) -> u8 { + *self as u8 + } +} + +#[derive(Copy, Clone)] +pub enum CodingRate { + Cr5 = 0x01, + Cr6 = 0x02, + Cr7 = 0x03, + Cr8 = 0x04, +} + +impl CodingRate { + pub fn as_u8(&self) -> u8 { + *self as u8 + } +} + +#[derive(Copy, Clone)] +pub enum SpreadingFactor { + Sf7 = 0x07, + Sf8 = 0x08, + Sf9 = 0x09, + Sf10 = 0x0A, + Sf11 = 0x0B, + Sf12 = 0x0C, +} + +impl SpreadingFactor { + pub fn as_u8(&self) -> u8 { + *self as u8 + } +} + +#[derive(Copy, Clone)] +pub enum LoraMode { + Sleep = 0x80, + Standby = 0x81, + Tx = 0x83, + Rx = 0x85, + RxSingle = 0x86, + CadDetection = 0x87, + StandbyOokFsk = 0xC1, +} + +impl LoraMode { + pub fn as_u8(&self) -> u8 { + *self as u8 + } +} + +#[derive(Copy, Clone)] +pub enum DioFunction { + RxDone = 0x00, + TxDone = 0x01, +} + +impl DioFunction { + pub fn as_u8(&self) -> u8 { *self as u8 } +} + +trait ToFlag { + fn flag_enabled(&self, f : IrqFlagMasks) -> bool; +} + +#[derive(Copy, Clone)] +enum IrqFlagMasks { + CadDetected = 0x01, + FhssChangeChannel = 0x02, + CadDone = 0x04, + TxDone = 0x08, + ValidHeader = 0x10, + PayloadCrcError = 0x20, + RxDone = 0x40, + RxTimeout = 0x80, +} + +impl IrqFlagMasks { + pub fn as_u8(&self) -> u8 { *self as u8 } +} + +impl ToFlag for u8 { + fn flag_enabled(&self, f : IrqFlagMasks) -> bool { + self & f.as_u8() != 0 + } +} + +pub enum RF95EventType { + None, + DataReceived, + DataSent, + ErrorPinConfig, + ErrorTimedOut, + ErrorWrongCrc, + ErrorCommBus, +} + +pub struct RF95 { + ch : Channel, + bw : Bandwidth, + cr : CodingRate, + sf : SpreadingFactor, + crc_check_enabled : bool, + implicit_header_enabled : bool, + pwr_db : u8, + thread_run : std::sync::Arc<AtomicBool>, + thread_handle : Option<std::thread::JoinHandle<()>>, + + rst_pin : Pin, +} + +impl RF95 { + pub fn new(bw : Bandwidth, cr : CodingRate, sf : SpreadingFactor) -> io::Result<RF95> { + let tmp_rst_pin = Pin::new(RST_BCM_PIN); + tmp_rst_pin.set_direction(Direction::Low).unwrap(); + thread::sleep(Duration::from_millis(10)); + tmp_rst_pin.set_value(1).unwrap(); + + Ok( + RF95 { + ch : Channel::Ch10, + bw, + cr, + sf, + crc_check_enabled : false, + implicit_header_enabled : false, + pwr_db : 0, + thread_run : std::sync::Arc::new(AtomicBool::new(false)), + thread_handle : None, + rst_pin : tmp_rst_pin, + } + ) + } + + pub fn get_version(&mut self) -> io::Result<u8> { + let device_version = RF95::read_register(LoraRegister::RegVersion)?; + Ok(device_version) + } + + pub fn set_main_parameters(&mut self, + ch : Channel, + bw : Bandwidth, + cr : CodingRate, + sf : SpreadingFactor) -> io::Result<()> { + self.set_channel(ch)?; + self.set_bandwidth(bw)?; + self.set_coding_rate(cr)?; + self.set_spreading_factor(sf) + } + + pub fn set_channel(&mut self, ch : Channel) -> io::Result<()> { + self.set_mode(LoraMode::Sleep)?; + self.ch = ch; + RF95::write_register(LoraRegister::RegFrfMsb, ch.msb())?; + RF95::write_register(LoraRegister::RegFrfMid, ch.mid())?; + RF95::write_register(LoraRegister::RegFrfLsb, ch.lsb()) + } + + pub fn set_spreading_factor(&mut self, sf : SpreadingFactor) -> io::Result<()> { + self.set_mode(LoraMode::Sleep)?; + self.sf = sf; + let mut tmp = RF95::read_register(LoraRegister::RegModemConfig2)?; + tmp &= 0x0F; + tmp |= sf.as_u8() << 4; + RF95::write_register(LoraRegister::RegModemConfig2, tmp) + } + + pub fn set_bandwidth(&mut self, bw : Bandwidth) -> io::Result<()> { + self.set_mode(LoraMode::Sleep)?; + self.bw = bw; + let mut tmp = RF95::read_register(LoraRegister::RegModemConfig1)?; + tmp &= 0x0F; + tmp |= bw.as_u8() << 4; + RF95::write_register(LoraRegister::RegModemConfig1, tmp)?; + Ok(()) + } + + pub fn set_coding_rate(&mut self, cr : CodingRate) -> io::Result<()> { + self.set_mode(LoraMode::Sleep)?; + self.cr = cr; + let mut tmp = RF95::read_register(LoraRegister::RegModemConfig1)?; + tmp &= 0xF1; + tmp |= cr.as_u8() << 1; + RF95::write_register(LoraRegister::RegModemConfig1, tmp) + } + + pub fn enable_crc_check(&mut self, en : bool) -> io::Result<()> { + let mut tmp = RF95::read_register(LoraRegister::RegModemConfig2)?; + if en { + tmp |= 1 << 2; + } else { + tmp &= !(1 << 2); + } + self.crc_check_enabled = en; + RF95::write_register(LoraRegister::RegModemConfig2, tmp) + } + + pub fn enable_implicit_header(&mut self, en : bool) -> io::Result<()> { + let mut tmp = RF95::read_register(LoraRegister::RegModemConfig1)?; + if en { + tmp |= 0x01; + } else { + tmp &= !0x01; + } + self.implicit_header_enabled = en; + RF95::write_register(LoraRegister::RegModemConfig1, tmp) + } + + pub fn set_output_power(&mut self, pwr : u8) -> io::Result<()> { + let mut pwr = pwr; + if pwr > 20 { + pwr = 20; + } + self.pwr_db = pwr; + let out = (pwr - 2) & 0x0F; + let mut tmp = RF95::read_register(LoraRegister::RegPaConfig)?; + tmp |= 0x80; + tmp &= 0xF0; + tmp |= out & 0x0F; + RF95::write_register(LoraRegister::RegPaConfig, tmp) + } + + pub fn set_mode(&mut self, m : LoraMode) -> io::Result<()> { + RF95::write_register(LoraRegister::RegOpMode, m.as_u8()) + } + + pub fn listen_timed(&mut self, timeout : u32) -> io::Result<Receiver<RF95EventType>> { + let (sender, receiver) = mpsc::channel(); + let input = Pin::new(DIO_BCM_PIN); + + + + self.thread_run.store(true, Ordering::SeqCst); + let run = self.thread_run.clone(); + + self.thread_handle = Some(thread::spawn(move || { + input.with_exported(|| { + let timeout = std::time::Duration::from_secs(timeout as u64); + let start = std::time::Instant::now(); + match input.set_direction(Direction::In) { + Ok(_) => (), + Err(e) => { + sender.send(RF95EventType::ErrorPinConfig).unwrap(); + panic!("Error while setting DI0 pin direction : {:?}", e); + }, + }; + + match input.set_edge(Edge::RisingEdge) { + Ok(_) => (), + Err(e) => { + sender.send(RF95EventType::ErrorPinConfig).unwrap(); + panic!("Error while setting DI0 pin edge detection : {:?}", e); + } + }; + + let mut poller = match input.get_poller() { + Ok(p) => p, + Err(e) => { + sender.send(RF95EventType::ErrorPinConfig).unwrap(); + panic!("Error while creating poller on DI0 : {:?}", e); + } + }; + + while run.load(Ordering::SeqCst) { + match poller.poll(10).unwrap() { + Some(_) => { + let mut regv = match RF95::read_register(LoraRegister::RegIrqFlags) { + Ok(r) => r, + Err(_) => { + sender.send(RF95EventType::ErrorCommBus).unwrap(); + return Err(sysfs_gpio::Error::from(io::Error::new(io::ErrorKind::Other, format!("Reading irq flag register")))); + }, + }; + if regv.flag_enabled(IrqFlagMasks::CadDetected) { + regv = regv & !IrqFlagMasks::CadDetected.as_u8(); + } + if regv.flag_enabled(IrqFlagMasks::CadDone) { + regv = regv & !IrqFlagMasks::CadDone.as_u8(); + } + if regv.flag_enabled(IrqFlagMasks::FhssChangeChannel) { + regv = regv & !IrqFlagMasks::FhssChangeChannel.as_u8(); + } + if regv.flag_enabled(IrqFlagMasks::PayloadCrcError) { + sender.send(RF95EventType::ErrorWrongCrc).unwrap(); + regv = regv & !IrqFlagMasks::PayloadCrcError.as_u8(); + } + if regv.flag_enabled(IrqFlagMasks::RxDone) { + sender.send(RF95EventType::DataSent).unwrap(); + regv = regv & !IrqFlagMasks::RxDone.as_u8(); + } + if regv.flag_enabled(IrqFlagMasks::TxDone) { + sender.send(RF95EventType::DataReceived).unwrap(); + regv = regv & !IrqFlagMasks::TxDone.as_u8(); + } + if regv.flag_enabled(IrqFlagMasks::RxTimeout) { + sender.send(RF95EventType::ErrorTimedOut).unwrap(); + regv = regv & !IrqFlagMasks::RxTimeout.as_u8(); + } + if regv.flag_enabled(IrqFlagMasks::ValidHeader) { + regv = regv & !IrqFlagMasks::ValidHeader.as_u8(); + } + match RF95::write_register(LoraRegister::RegIrqFlags, regv) { + Ok(_) => (), + Err(_) => { + sender.send(RF95EventType::ErrorCommBus).unwrap(); + return Err(sysfs_gpio::Error::from(io::Error::new(io::ErrorKind::Other, format!("Reading irq flag register")))); + }, + }; + }, + None => (), + }; + if timeout.as_secs() > 0 { + if std::time::Instant::now().duration_since(start) > timeout { + break; + } + } + } + Ok(()) + }).expect("Cannot export gpio"); + })); + + Ok(receiver) + } + + pub fn listen_continuous(&mut self) -> io::Result<Receiver<RF95EventType>> { + self.listen_timed(0) + } + + pub fn stop_listening(&mut self) -> Result<(), String> { + self.thread_run.store(false, Ordering::SeqCst); + match self.thread_handle.take() { + Some(th) => { + match th.join() { + Ok(_) => return Ok(()), + Err(_) => return Err(format!("Cannot join spawned thread")), + }; + }, + None => return Err(format!("No thread spawned")), + }; + } + + pub fn get_snr(&mut self) -> io::Result<i16> { + Ok((RF95::read_register(LoraRegister::RegPktSnrValue)? as i16) / 4) + } + + pub fn get_packet_rssi(&mut self) -> io::Result<i16> { + Ok((RF95::read_register(LoraRegister::RegRssiValue)? as i16) - 137) + } + + pub fn get_rssi(&mut self) -> io::Result<i16> { + Ok((RF95::read_register(LoraRegister::RegRssiValue)? as i16) - 137) + } + + pub fn reset(&mut self) -> io::Result<()> { + match self.rst_pin.set_direction(Direction::Low) { + Ok(_) => (), + Err(_) => return Err(std::io::Error::new(ErrorKind::Other, "Problem setting value on gpio")), + }; + std::thread::sleep(Duration::new(0, 10000000)); + match self.rst_pin.set_value(1) { + Ok(_) => return Ok(()), + Err(_) => return Err(std::io::Error::new(ErrorKind::Other, "Problem setting value on gpio")), + }; + } + + pub fn set_dio_mapping(&mut self, df : DioFunction) -> io::Result<()> { + let prev_mode = RF95::read_register(LoraRegister::RegOpMode)?; + self.set_mode(LoraMode::StandbyOokFsk)?; + let mut tmp = RF95::read_register(LoraRegister::RegDioMapping1)?; + tmp &= 0x3F; + if df.as_u8() == DioFunction::TxDone.as_u8() { + tmp |= 0x40; + } + RF95::write_register(LoraRegister::RegDioMapping1, tmp)?; + RF95::write_register(LoraRegister::RegOpMode, prev_mode) + } + + fn write_register(reg : LoraRegister, data : u8) -> io::Result<()> { + let mut spi = Spidev::open("/dev/spidev0.0")?; + let spi_options = SpidevOptions::new() + .bits_per_word(8) + .max_speed_hz(5_000_000) + .mode(SPI_MODE_0) + .build(); + spi.configure(&spi_options)?; + + match spi.write(&[reg.as_u8(), data]) { + Ok(_) => Ok(()), + Err(_) => Err(io::Error::new(ErrorKind::Other, "Problem while writing to device")) + } + } + + fn write_buffer(reg : LoraRegister, buffer : Vec<u8>) -> io::Result<()> { + let mut spi = Spidev::open("/dev/spidev0.0")?; + let spi_options = SpidevOptions::new() + .bits_per_word(8) + .max_speed_hz(5_000_000) + .mode(SPI_MODE_0) + .build(); + spi.configure(&spi_options)?; + + let cs_pin = Pin::new(CS_BCM_PIN); + cs_pin.set_direction(Direction::High).unwrap(); + + let mut v2 = buffer; + v2.insert(0, reg.as_u8()); + cs_pin.set_value(0).unwrap(); + spi.write(&v2)?; + match cs_pin.set_value(1) { + Ok(_) => Ok(()), + Err(_) => Err(std::io::Error::new(ErrorKind::Other, "Problem setting value on gpio")), + } + } + + fn read_register(reg : LoraRegister) -> io::Result<u8> { + let mut spi = Spidev::open("/dev/spidev0.0")?; + let spi_options = SpidevOptions::new() + .bits_per_word(8) + .max_speed_hz(5_000_000) + .mode(SPI_MODE_0) + .build(); + spi.configure(&spi_options)?; + + let cs_pin = Pin::new(CS_BCM_PIN); + cs_pin.set_direction(Direction::High).unwrap(); + + let mut ret: [u8; 1] = [0; 1]; + cs_pin.set_value(0).unwrap(); + spi.write(&[reg.as_u8()])?; + spi.read(&mut ret).unwrap(); + match cs_pin.set_value(1) { + Ok(_) => (), + Err(_) => return Err(io::Error::new(ErrorKind::Other, "Problem setting value on gpio")), + }; + Ok(ret[0]) + } + + fn read_buffer(reg : LoraRegister, buffer : &mut Vec<u8>, length : u8) -> io::Result<()> { + let mut spi = Spidev::open("/dev/spidev0.0")?; + let spi_options = SpidevOptions::new() + .bits_per_word(8) + .max_speed_hz(5_000_000) + .mode(SPI_MODE_0) + .build(); + spi.configure(&spi_options)?; + + let cs_pin = Pin::new(CS_BCM_PIN); + cs_pin.set_direction(Direction::High).unwrap(); + + let mut tmp : Vec<u8> = Vec::with_capacity(length as usize); + cs_pin.set_value(0).unwrap(); + spi.write(&[reg.as_u8()])?; + spi.read(tmp.as_mut_slice())?; + buffer.clear(); + buffer.write(&tmp)?; + cs_pin.set_value(1).unwrap(); + Ok(()) + } +} |