diff options
Diffstat (limited to 'kicad')
| -rw-r--r-- | kicad/picardy.kicad_pro | 70 |
1 files changed, 53 insertions, 17 deletions
diff --git a/kicad/picardy.kicad_pro b/kicad/picardy.kicad_pro index 4f0fe99..e1003d5 100644 --- a/kicad/picardy.kicad_pro +++ b/kicad/picardy.kicad_pro @@ -1,5 +1,6 @@ { "board": { + "3dviewports": [], "design_settings": { "defaults": { "board_outline_line_width": 0.049999999999999996, @@ -136,7 +137,8 @@ "zones_allow_external_fillets": false, "zones_use_no_outline": true }, - "layer_presets": [] + "layer_presets": [], + "viewports": [] }, "boards": [], "cvpcb": { @@ -320,18 +322,23 @@ "rule_severities": { "bus_definition_conflict": "error", "bus_entry_needed": "error", - "bus_label_syntax": "error", "bus_to_bus_conflict": "error", "bus_to_net_conflict": "error", + "conflicting_netclasses": "error", "different_unit_footprint": "error", "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", + "endpoint_off_grid": "warning", "extra_units": "error", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", "lib_symbol_issues": "warning", + "missing_bidi_pin": "warning", + "missing_input_pin": "warning", + "missing_power_pin": "error", + "missing_unit": "warning", "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", @@ -341,6 +348,7 @@ "pin_to_pin": "warning", "power_pin_not_driven": "error", "similar_labels": "warning", + "simulation_model_issue": "error", "unannotated": "error", "unit_value_mismatch": "error", "unresolved_variable": "error", @@ -358,7 +366,7 @@ "net_settings": { "classes": [ { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, @@ -372,10 +380,10 @@ "track_width": 0.2, "via_diameter": 0.8, "via_drill": 0.4, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, @@ -384,27 +392,49 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Power", - "nets": [ - "+12V", - "+3V3", - "+5VA", - "+8V", - "+8VRX", - "+8VTX", - "GND" - ], "pcb_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.8, "via_diameter": 0.8, "via_drill": 0.6, - "wire_width": 6.0 + "wire_width": 6 } ], "meta": { - "version": 2 + "version": 3 }, - "net_colors": null + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [ + { + "netclass": "Power", + "pattern": "+12V" + }, + { + "netclass": "Power", + "pattern": "+3V3" + }, + { + "netclass": "Power", + "pattern": "+5VA" + }, + { + "netclass": "Power", + "pattern": "+8V" + }, + { + "netclass": "Power", + "pattern": "+8VRX" + }, + { + "netclass": "Power", + "pattern": "+8VTX" + }, + { + "netclass": "Power", + "pattern": "GND" + } + ] }, "pcbnew": { "last_paths": { @@ -420,6 +450,8 @@ "schematic": { "annotate_start_num": 0, "drawing": { + "dashed_lines_dash_length_ratio": 12.0, + "dashed_lines_gap_length_ratio": 3.0, "default_line_thickness": 6.0, "default_text_size": 50.0, "field_names": [], @@ -451,7 +483,11 @@ "page_layout_descr_file": "", "plot_directory": "out", "spice_adjust_passive_values": false, + "spice_current_sheet_as_root": false, "spice_external_command": "spice \"%I\"", + "spice_model_current_sheet_as_root": true, + "spice_save_all_currents": false, + "spice_save_all_voltages": false, "subpart_first_id": 65, "subpart_id_separator": 0 }, |