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authorMatthias P. Braendli <matthias.braendli@mpb.li>2021-06-04 21:40:42 +0200
committerMatthias P. Braendli <matthias.braendli@mpb.li>2021-06-04 21:40:42 +0200
commitaa2721cc8d0f71145e86019ef367377bd650fc0b (patch)
tree03a3e2ae64ac29dc4031c71fbd88cc4402f11d6f /sw
parent71f560ad84328453e75c9c7112003f76ea804684 (diff)
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Port some fixes from eval-clock to picardy
Diffstat (limited to 'sw')
-rw-r--r--sw/picardy/src/main.rs2
-rw-r--r--sw/picardy/src/si_clock.rs15
2 files changed, 12 insertions, 5 deletions
diff --git a/sw/picardy/src/main.rs b/sw/picardy/src/main.rs
index 9427c2b..b6bf098 100644
--- a/sw/picardy/src/main.rs
+++ b/sw/picardy/src/main.rs
@@ -490,6 +490,7 @@ fn TIM2() {
}
}
+#[allow(non_snake_case)]
#[cortex_m_rt::exception]
fn HardFault(ef: &ExceptionFrame) -> ! {
let periph = unsafe { cortex_m::Peripherals::steal() };
@@ -501,6 +502,7 @@ fn HardFault(ef: &ExceptionFrame) -> ! {
loop { }
}
+#[allow(non_snake_case)]
#[cortex_m_rt::exception]
fn DefaultHandler(irqn: i16) {
hprintln!("Unhandled exception (IRQn = {})", irqn).unwrap();
diff --git a/sw/picardy/src/si_clock.rs b/sw/picardy/src/si_clock.rs
index a4b0e7a..6de4c25 100644
--- a/sw/picardy/src/si_clock.rs
+++ b/sw/picardy/src/si_clock.rs
@@ -84,12 +84,17 @@ fn set_bfo(siclock: &mut dyn Si5351, freq: u32) -> Result<(), si5351::Error>
fn set_vfo(siclock: &mut dyn Si5351, freq: u32)
{
- let (div, mult, num, denom) = clock_settings_with_pll_calculation(freq);
+ if freq == 0 {
+ siclock.set_clock_enabled(si5351::ClockOutput::Clk0, false);
+ }
+ else {
+ let (div, mult, num, denom) = clock_settings_with_pll_calculation(freq);
- siclock.setup_pll(si5351::PLL::B, mult, num, denom).unwrap();
- siclock.setup_multisynth_int(si5351::Multisynth::MS0, div, si5351::OutputDivider::Div1).unwrap();
- siclock.select_clock_pll(si5351::ClockOutput::Clk0, si5351::PLL::B);
- siclock.set_clock_enabled(si5351::ClockOutput::Clk0, true);
+ siclock.setup_pll(si5351::PLL::B, mult, num, denom).unwrap();
+ siclock.setup_multisynth_int(si5351::Multisynth::MS0, div, si5351::OutputDivider::Div1).unwrap();
+ siclock.select_clock_pll(si5351::ClockOutput::Clk0, si5351::PLL::B);
+ siclock.set_clock_enabled(si5351::ClockOutput::Clk0, true);
+ }
siclock.flush_clock_control(si5351::ClockOutput::Clk0).unwrap();
}