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authorMatthias P. Braendli <matthias.braendli@mpb.li>2023-01-09 18:07:14 +0100
committerMatthias P. Braendli <matthias.braendli@mpb.li>2023-01-09 18:07:14 +0100
commit09fe7720e68f94b5bf4084a97a920bfe30852605 (patch)
tree53206aa863cc806c6ad2fdb70a002042c2a5f4a2 /sw
parent72400df18f27ef370380651a6436637d48c2e18b (diff)
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Do some schematic changes
Diffstat (limited to 'sw')
-rw-r--r--sw/picardy/src/cw.rs69
1 files changed, 68 insertions, 1 deletions
diff --git a/sw/picardy/src/cw.rs b/sw/picardy/src/cw.rs
index 045ef15..508b939 100644
--- a/sw/picardy/src/cw.rs
+++ b/sw/picardy/src/cw.rs
@@ -10,13 +10,80 @@ use stm32f1xx_hal::{
pwm,
};
+const CW_MAPPING : [u8; 50] = [ //{{{
+ // Read bits from right to left
+
+ 0b110101, //+ ASCII 43
+ 0b110101, //, ASCII 44
+ 0b1011110, //- ASCII 45
+
+ 0b1010101, //., ASCII 46
+ 0b110110, // / ASCII 47
+
+ 0b100000, // 0, ASCII 48
+ 0b100001, // 1
+ 0b100011,
+ 0b100111,
+ 0b101111,
+ 0b111111,
+ 0b111110,
+ 0b111100,
+ 0b111000,
+ 0b110000, // 9, ASCII 57
+
+ // The following are mostly invalid, but
+ // required to fill the gap in ASCII between
+ // numerals and capital letters
+ 0b10, // :
+ 0b10, // ;
+ 0b10, // <
+ 0b101110, // =
+ 0b10, // >
+ 0b1110011, // ?
+ 0b1101001, //@
+
+ 0b101, // A ASCII 65
+ 0b11110,
+ 0b11010,
+ 0b1110,
+ 0b11,
+ 0b11011,
+ 0b1100,
+ 0b11111,
+ 0b111,
+ 0b10001,
+ 0b1010,
+ 0b11101,
+ 0b100, //M
+ 0b110,
+ 0b1000,
+ 0b11001,
+ 0b10100,
+ 0b1101,
+ 0b1111,
+ 0b10,
+ 0b1011,
+ 0b10111,
+ 0b1001,
+ 0b10110,
+ 0b10010,
+ 0b11100, // Z
+
+ 0b101010, //Start, ASCII [
+ 0b1010111, // SK , ASCII '\'
+]; //}}}
+
+const CW_MACRO : &[u8; 28] = b"CQ DE HB9EGM HB9EGM HB9EGM K";
+
+const SIDETONE_FREQ : u32 = 800;
+
pub struct CWPWM {
channel : pwm::PwmChannel<TIM1, pwm::C1>,
}
impl CWPWM {
pub fn new(pa8: PA8<Alternate<PushPull>>, tim1: timer::Timer<TIM1>, mapr: &mut MAPR) -> Self {
- let pwm = tim1.pwm(pa8, mapr, 400.hz());
+ let pwm = tim1.pwm(pa8, mapr, SIDETONE_FREQ.hz());
let mut channel = pwm.split();
channel.enable();
channel.set_duty(0);