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| author | Matthias P. Braendli <matthias.braendli@mpb.li> | 2021-03-20 11:45:23 +0100 |
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| committer | Matthias P. Braendli <matthias.braendli@mpb.li> | 2021-03-20 11:45:23 +0100 |
| commit | 2071c8485241e0b95de891e8855542d7c51915ab (patch) | |
| tree | 77a634e97775b3552705855a60f6b4eadc7de2ac /sw/eval-clock-cw-tx/.gdbinit | |
| parent | 336048a49af662684a76871a4974f8fb93239b99 (diff) | |
| download | picardy-2071c8485241e0b95de891e8855542d7c51915ab.tar.gz picardy-2071c8485241e0b95de891e8855542d7c51915ab.tar.bz2 picardy-2071c8485241e0b95de891e8855542d7c51915ab.zip | |
Create eval-clock-cw-tx sw
Diffstat (limited to 'sw/eval-clock-cw-tx/.gdbinit')
| -rw-r--r-- | sw/eval-clock-cw-tx/.gdbinit | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/sw/eval-clock-cw-tx/.gdbinit b/sw/eval-clock-cw-tx/.gdbinit new file mode 100644 index 0000000..08b6398 --- /dev/null +++ b/sw/eval-clock-cw-tx/.gdbinit @@ -0,0 +1,18 @@ +target remote :3333 + +monitor arm semihosting enable + +# # send captured ITM to the file itm.fifo +# # (the microcontroller SWO pin must be connected to the programmer SWO pin) +# # 8000000 must match the core clock frequency +# monitor tpiu config internal itm.fifo uart off 8000000 + +# # OR: make the microcontroller SWO pin output compatible with UART (8N1) +# # 2000000 is the frequency of the SWO pin +# monitor tpiu config external uart off 8000000 2000000 + +# # enable ITM port 0 +# monitor itm port 0 on + +#load +#step |