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authorMatthias P. Braendli <matthias.braendli@mpb.li>2020-06-29 21:06:02 +0200
committerMatthias P. Braendli <matthias.braendli@mpb.li>2020-06-29 21:06:02 +0200
commit10c64cc56fd86c3ac94c0565fcf9e20272987577 (patch)
tree3c5ff7568f7b84f8d5ff960fe417af79af6db30c /sw/demo1/src
parent19999214aab4ededaee069677e6ae73e2ef254ec (diff)
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Set VFO with encoder
Diffstat (limited to 'sw/demo1/src')
-rw-r--r--sw/demo1/src/main.rs71
1 files changed, 28 insertions, 43 deletions
diff --git a/sw/demo1/src/main.rs b/sw/demo1/src/main.rs
index a45c0bb..093df4f 100644
--- a/sw/demo1/src/main.rs
+++ b/sw/demo1/src/main.rs
@@ -1,6 +1,8 @@
#![no_main]
#![no_std]
+const REF_CLOCK : u32 = 25_000_000;
+
use core::convert::TryInto;
use cortex_m_rt::ExceptionFrame;
@@ -42,7 +44,7 @@ fn clock_settings_for_pll(freq: u32, pll: u32) -> (u16, u32, u32) {
(a.try_into().unwrap(), b, c)
}
-fn clock_settings_with_pll_calculation(freq: u32, ref_clock: u32) -> (u16, u8, u32, u32) {
+fn clock_settings_with_pll_calculation(freq: u32) -> (u16, u8, u32, u32) {
let mut divider : u32 = 900_000_000 / freq; // Calculate the division ratio. 900,000,000 is the maximum internal
if (divider % 2) == 1 {
@@ -51,11 +53,11 @@ fn clock_settings_with_pll_calculation(freq: u32, ref_clock: u32) -> (u16, u8, u
let pll_freq = divider * freq;
// mult is an integer that must be in the range 15..90
- let mult = pll_freq / ref_clock;
- let l = pll_freq % ref_clock;
+ let mult = pll_freq / REF_CLOCK;
+ let l = pll_freq % REF_CLOCK;
let denom = 1048575;
- let num = f64::from(l) * f64::from(denom) / f64::from(ref_clock);
+ let num = f64::from(l) * f64::from(denom) / f64::from(REF_CLOCK);
(divider.try_into().unwrap(), mult.try_into().unwrap(), num as u32, denom)
}
@@ -74,6 +76,19 @@ fn print(step: usize) -> Result<(), core::fmt::Error> {
Ok(())
}
+fn set_vfo(freq: u32, siclock: &mut dyn Si5351)
+{
+ let (div, mult, num, denom) = clock_settings_with_pll_calculation(freq);
+
+ siclock.setup_pll(si5351::PLL::B, mult, num, denom).unwrap();
+ siclock.setup_multisynth_int(si5351::Multisynth::MS0, div, si5351::OutputDivider::Div1).unwrap();
+
+ siclock.select_clock_pll(si5351::ClockOutput::Clk0, si5351::PLL::B);
+ siclock.set_clock_enabled(si5351::ClockOutput::Clk0, true);
+ siclock.flush_clock_control(si5351::ClockOutput::Clk0).unwrap();
+}
+
+
#[cortex_m_rt::entry]
fn main() -> ! {
let cp = cortex_m::Peripherals::take().unwrap();
@@ -158,8 +173,7 @@ fn main() -> ! {
lcd.set_cursor_pos(0, &mut delay).unwrap();
lcd.write_str("Hello, world!", &mut delay).unwrap();
- let ref_clock = 25_000_000;
- let mut siclock = Si5351Device::new(i2c_busmanager.acquire(), false, ref_clock);
+ let mut siclock = Si5351Device::new(i2c_busmanager.acquire(), false, REF_CLOCK);
siclock.init(si5351::CrystalLoad::_10).unwrap();
// See freqplan.py for Si5351 frequency plan
@@ -169,7 +183,7 @@ fn main() -> ! {
{
let clk1 = 116_000_000;
- let (a, b, c) = clock_settings_for_pll(clk1, pll_a_mult * ref_clock);
+ let (a, b, c) = clock_settings_for_pll(clk1, pll_a_mult * REF_CLOCK);
siclock.setup_multisynth(si5351::Multisynth::MS1, a, b, c, si5351::OutputDivider::Div1).unwrap();
siclock.select_clock_pll(si5351::ClockOutput::Clk1, si5351::PLL::A);
siclock.set_clock_enabled(si5351::ClockOutput::Clk1, true);
@@ -178,7 +192,7 @@ fn main() -> ! {
{
let clk2 = 4_195_210;
- let (a, b, c) = clock_settings_for_pll(clk2, pll_a_mult * ref_clock);
+ let (a, b, c) = clock_settings_for_pll(clk2, pll_a_mult * REF_CLOCK);
siclock.setup_multisynth(si5351::Multisynth::MS2, a, b, c, si5351::OutputDivider::Div1).unwrap();
siclock.select_clock_pll(si5351::ClockOutput::Clk2, si5351::PLL::A);
siclock.set_clock_enabled(si5351::ClockOutput::Clk2, true);
@@ -187,18 +201,7 @@ fn main() -> ! {
siclock.reset_pll(si5351::PLL::A).unwrap();
- {
- let clk0 = 23_000_000;
-
- let (div, mult, num, denom) = clock_settings_with_pll_calculation(clk0, ref_clock);
-
- siclock.setup_pll(si5351::PLL::B, mult, num, denom).unwrap();
- siclock.setup_multisynth_int(si5351::Multisynth::MS0, div, si5351::OutputDivider::Div1).unwrap();
-
- siclock.select_clock_pll(si5351::ClockOutput::Clk0, si5351::PLL::B);
- siclock.set_clock_enabled(si5351::ClockOutput::Clk0, true);
- siclock.flush_clock_control(si5351::ClockOutput::Clk0).unwrap();
- }
+ set_vfo(23_000_000, &mut siclock);
siclock.reset_pll(si5351::PLL::B).unwrap();
@@ -219,7 +222,11 @@ fn main() -> ! {
let mut string = arrayvec::ArrayString::<[_; 16]>::new();
let encoder_count = qei.count();
if encoder_count != last_encoder_count {
- write!(string, "Enc {} ", encoder_count).unwrap();
+ let freq = 23_000_000 + encoder_count as u32;
+
+ set_vfo(freq, &mut siclock);
+
+ write!(string, "{} ", freq).unwrap();
lcd.write_str(&string, &mut delay).unwrap();
}
last_encoder_count = encoder_count;
@@ -255,25 +262,3 @@ fn DefaultHandler(irqn: i16) {
cortex_m::asm::bkpt();
loop { }
}
-
-
-
- /* code to discover i2c device address
- let mut stdout = hio::hstdout().unwrap();
-
- loop {
- for addr in 0..127usize {
- let bytes = [0u8; 1];
- let mut buffer = [0u8; 1];
- match i2c.write_read(addr as u8, &bytes, &mut buffer) {
- Ok(()) => {
- write!(stdout, "{}: {}\n", addr, buffer[0]).unwrap();
- },
- Err(_) => {
- write!(stdout, "{}: fail\n", addr).unwrap();
- },
- }
- }
- }
- */
-