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| author | Matthias P. Braendli <matthias.braendli@mpb.li> | 2020-06-28 16:42:21 +0200 |
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| committer | Matthias P. Braendli <matthias.braendli@mpb.li> | 2020-06-28 16:42:21 +0200 |
| commit | 5d1cff57f9f5acd740a8b5f8c941beefdcc00176 (patch) | |
| tree | bdfd0e394d6333aead7d3a0295ba3457bd68275d /sw/demo1/.gdbinit | |
| parent | 93220f99a52dc93f9a2d5b11074f60156ef70210 (diff) | |
| download | picardy-5d1cff57f9f5acd740a8b5f8c941beefdcc00176.tar.gz picardy-5d1cff57f9f5acd740a8b5f8c941beefdcc00176.tar.bz2 picardy-5d1cff57f9f5acd740a8b5f8c941beefdcc00176.zip | |
sw: configure si5351
Diffstat (limited to 'sw/demo1/.gdbinit')
| -rw-r--r-- | sw/demo1/.gdbinit | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/sw/demo1/.gdbinit b/sw/demo1/.gdbinit new file mode 100644 index 0000000..08b6398 --- /dev/null +++ b/sw/demo1/.gdbinit @@ -0,0 +1,18 @@ +target remote :3333 + +monitor arm semihosting enable + +# # send captured ITM to the file itm.fifo +# # (the microcontroller SWO pin must be connected to the programmer SWO pin) +# # 8000000 must match the core clock frequency +# monitor tpiu config internal itm.fifo uart off 8000000 + +# # OR: make the microcontroller SWO pin output compatible with UART (8N1) +# # 2000000 is the frequency of the SWO pin +# monitor tpiu config external uart off 8000000 2000000 + +# # enable ITM port 0 +# monitor itm port 0 on + +#load +#step |