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authorMatthias P. Braendli <matthias.braendli@mpb.li>2023-03-25 22:24:51 +0100
committerMatthias P. Braendli <matthias.braendli@mpb.li>2023-03-25 22:24:51 +0100
commit59366778836025e89550a1d641c8bd613dccaffb (patch)
tree2510ee79e9c62bf367ccb327c51e3ed32021bc96 /sw/dart-70
parentd74ecf74a6026d43d2dfe611df14c19833e6cc83 (diff)
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Fix DART-70 things seen during assembly
Diffstat (limited to 'sw/dart-70')
-rw-r--r--sw/dart-70/src/si_clock.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/sw/dart-70/src/si_clock.rs b/sw/dart-70/src/si_clock.rs
index 6de4c25..1f97a0a 100644
--- a/sw/dart-70/src/si_clock.rs
+++ b/sw/dart-70/src/si_clock.rs
@@ -107,7 +107,7 @@ impl<I2C, E> SiClock<I2C>
I2C: WriteRead<Error = E> + Write<Error = E>,
{
pub fn new(i2c: I2C, bfo: u32, vfo: u32) -> SiClock<I2C> {
- let mut siclock = Si5351Device::new(i2c, false, REF_CLOCK);
+ let mut siclock = Si5351Device::new(i2c, false);
siclock.init(si5351::CrystalLoad::_10).unwrap();
// See freqplan.py for Si5351 frequency plan