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authorMatthias P. Braendli <matthias.braendli@mpb.li>2024-01-31 23:18:07 +0100
committerMatthias P. Braendli <matthias.braendli@mpb.li>2024-01-31 23:18:07 +0100
commitd45189798c160cee329b7c59636b0caf538244f6 (patch)
treeeee15c379f3be80e46eb08626b68bbd96d618151 /sw/dart-70/src/state.rs
parent98ba4a9c42fa946f26b2a6ffce98c03436c6dd2d (diff)
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DART-70: get VOX and CW workingHEADmaster
Diffstat (limited to 'sw/dart-70/src/state.rs')
-rw-r--r--sw/dart-70/src/state.rs33
1 files changed, 12 insertions, 21 deletions
diff --git a/sw/dart-70/src/state.rs b/sw/dart-70/src/state.rs
index d5d4bf3..ffde88a 100644
--- a/sw/dart-70/src/state.rs
+++ b/sw/dart-70/src/state.rs
@@ -1,5 +1,6 @@
pub const VHF_BAND_EDGE : u32 = 70_000_000;
pub const VHF_INITIAL_VFO : u32 = 70_200_000;
+pub const VFO_FREQ_ERROR : i32 = 2_000; // measured at 70.2 MHz
// Values below are measured with the assembled XTAL filter
pub const XTAL_FILT_FREQ : u32 = 11_057_500;
pub const BFO_LSB : u32 = XTAL_FILT_FREQ + 1_400;
@@ -38,6 +39,7 @@ pub enum Mode {
USB,
CustomShift(u32),
CW(CWMode),
+ DIG,
}
#[derive(Clone, PartialEq, Eq)]
@@ -48,6 +50,8 @@ pub enum SequenceState {
TxSSB,
SwitchingCW,
TxCW,
+ SwitchingDIG,
+ TxDIG,
}
impl SequenceState {
@@ -89,19 +93,12 @@ impl State {
}
pub fn bfo(&self) -> u32 {
- if self.send_tone {
- 0
- }
- else {
- match self.mode {
- Mode::LSB => BFO_LSB,
- Mode::USB => BFO_USB,
- Mode::CustomShift(fs) => fs,
- Mode::CW(_) => match self.sequence_state {
- SequenceState::SwitchingCW | SequenceState::TxCW => 0,
- _ => BFO_CW,
- },
- }
+ match self.mode {
+ Mode::LSB => BFO_LSB,
+ Mode::USB => BFO_USB,
+ Mode::CustomShift(fs) => fs,
+ Mode::CW(_) => BFO_CW,
+ Mode::DIG => BFO_USB,
}
}
@@ -113,14 +110,8 @@ impl State {
}
pub fn vfo(&self) -> u32 {
- let cw_offset = match self.sequence_state {
- SequenceState::SwitchingCW | SequenceState::TxCW => 500,
- _ => 0,
- };
-
- let vfo = (self.vhf_qrg() - self.bfo()) as i32 +
- if self.sequence_state.apply_rit() { self.rit } else { 0 } +
- cw_offset;
+ let vfo = (self.vhf_qrg() - self.bfo()) as i32 + VFO_FREQ_ERROR +
+ if self.sequence_state.apply_rit() { self.rit } else { 0 };
vfo as u32
}
}