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| author | Matthias P. Braendli <matthias.braendli@mpb.li> | 2020-04-19 20:55:24 +0200 |
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| committer | Matthias P. Braendli <matthias.braendli@mpb.li> | 2020-04-19 20:55:24 +0200 |
| commit | ec330aa367bfb8b337df9a4f220c7909ef95e86c (patch) | |
| tree | 322b11b1b72f726c24d36d6bcab61b187db84144 /README.md | |
| parent | d547c5c5c9834dbb1dbe000b42e09b22f064f947 (diff) | |
| download | picardy-ec330aa367bfb8b337df9a4f220c7909ef95e86c.tar.gz picardy-ec330aa367bfb8b337df9a4f220c7909ef95e86c.tar.bz2 picardy-ec330aa367bfb8b337df9a4f220c7909ef95e86c.zip | |
Case edge alignment for connectors, add unused uC pins to header
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -15,6 +15,8 @@ combined with the [Anglian 3L transverter](http://www.g4ddk.com/Products.html). * Offer a 10MHz output refclk for a transverter * Instead, have a 25MHz ref input, and use a LeoBodnar reference +* Very good [explanations](https://groups.io/g/BITX20/topic/si5351a_facts_and_myths/5430607) about DDS vs DPLL from Hans Summers + TODO before ordering the PCB ============================ |