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| author | Matthias P. Braendli <matthias.braendli@mpb.li> | 2021-05-25 22:43:38 +0200 |
|---|---|---|
| committer | Matthias P. Braendli <matthias.braendli@mpb.li> | 2021-05-25 22:43:38 +0200 |
| commit | 809a06e18c583539a47575f70a876f9c99f0b1f6 (patch) | |
| tree | b5209975700e80fc5ba70c16d9449887218e0051 | |
| parent | ddfefa0ee832cce107de4201844282e6109ed7b6 (diff) | |
| download | picardy-809a06e18c583539a47575f70a876f9c99f0b1f6.tar.gz picardy-809a06e18c583539a47575f70a876f9c99f0b1f6.tar.bz2 picardy-809a06e18c583539a47575f70a876f9c99f0b1f6.zip | |
Change sysclk to 32MHz to avoid i2c noise at 144.320MHz
| -rw-r--r-- | sw/picardy/src/main.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sw/picardy/src/main.rs b/sw/picardy/src/main.rs index d354fbc..ad3cbd1 100644 --- a/sw/picardy/src/main.rs +++ b/sw/picardy/src/main.rs @@ -98,7 +98,7 @@ fn main() -> ! { let mut afio = dp.AFIO.constrain(&mut rcc.apb2); let clocks = rcc.cfgr .use_hse(16.mhz()) - .sysclk(48.mhz()) + .sysclk(32.mhz()) .pclk1(24.mhz()) .adcclk(2.mhz()) .freeze(&mut flash.acr); |