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authorMatthias P. Braendli <matthias.braendli@mpb.li>2020-11-29 22:24:40 +0100
committerMatthias P. Braendli <matthias.braendli@mpb.li>2020-11-29 22:24:40 +0100
commit0447d38e159daf293fc33a147c4e96a1cde5acfe (patch)
tree97ca2075a2c23b8a7c15a63eb189e1565e59049b
parentf984325944e3a8946c1de2e2b0039d4d7148186e (diff)
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Update firmware for new LO
-rw-r--r--freqplan.py6
-rw-r--r--sw/picardy/Makefile8
-rw-r--r--sw/picardy/src/main.rs20
-rw-r--r--sw/picardy/src/si_clock.rs11
4 files changed, 24 insertions, 21 deletions
diff --git a/freqplan.py b/freqplan.py
index 8ad520f..9272c41 100644
--- a/freqplan.py
+++ b/freqplan.py
@@ -1,4 +1,8 @@
#!/usr/bin/env python3
+#
+# OUTDATED
+# This document is outdated because the VHF LO is not generated
+# externally
from fractions import Fraction
from math import floor
@@ -6,7 +10,7 @@ from math import floor
xtal = 25
print()
-print("# 160MHz and 4.915 MHz on PLLa")
+print("# 116MHz and 4.915 MHz on PLLa")
PLLa = xtal * 32
print(f"PLLa = xtal * 32 = {PLLa} MHz")
diff --git a/sw/picardy/Makefile b/sw/picardy/Makefile
index 6dc5806..8c5fc79 100644
--- a/sw/picardy/Makefile
+++ b/sw/picardy/Makefile
@@ -1,17 +1,17 @@
.PHONY: all openocd debug
OPENOCD := openocd
-OPENOCD_CFG := /usr/share/openocd/scripts/target/stm32f1x.cfg
-BIN := target/thumbv7em-none-eabihf/release/picardy
+OPENOCD_OPT := -f interface/stlink-v2.cfg -f target/stm32f1x.cfg
+BIN := target/thumbv7m-none-eabi/debug/picardy
# Build and flash in release mode
all:
cargo build
- $(OPENOCD) -f $(OPENOCD_CFG) -c "program $(BIN) reset exit"
+ $(OPENOCD) $(OPENOCD_OPT) -c "program $(BIN) reset exit"
# Start a openocd session.
openocd:
- $(OPENOCD) -f $(OPENOCD_CFG)
+ $(OPENOCD) $(OPENOCD_OPT)
# Start a gdb session. Works if a valid openocd session is existing.
debug:
diff --git a/sw/picardy/src/main.rs b/sw/picardy/src/main.rs
index 66c00c5..e6d2469 100644
--- a/sw/picardy/src/main.rs
+++ b/sw/picardy/src/main.rs
@@ -67,6 +67,8 @@ enum FilterShift {
Custom(u32),
}
+const VHF_BAND_EDGE : u32 = 144_000_000;
+const VHF_LO : u32 = 114_286_000;
const BFO_LSB : u32 = 4_915_940;
const BFO_USB : u32 = 4_914_910;
@@ -74,7 +76,7 @@ struct State {
mode : Mode,
filter_shift : FilterShift,
bfo_tune_fail : bool,
- qrg : u32,
+ vhf_qrg : u32,
tune_speed : TuneSpeed,
transmit : bool,
@@ -89,8 +91,12 @@ impl State {
}
}
+ fn if_qrg(&self) -> u32 {
+ self.vhf_qrg - VHF_LO
+ }
+
fn vfo(&self) -> u32 {
- self.qrg - self.bfo()
+ self.if_qrg() - self.bfo()
}
fn vfo_incr(&self) -> i32 {
@@ -138,9 +144,11 @@ fn update_disp<T: hd44780_driver::bus::DataBus>(lcd: &mut HD44780<T>, state: &St
lcd.write_str(&string, delay).unwrap();
string.clear();
+ /* Shorten the QRG to avoid using three digits for nothing */
+ let disp_freq = (state.vhf_qrg as i32) - (VHF_BAND_EDGE as i32);
match state.mode {
- Mode::BFO => write!(string, " {:<10}", state.qrg).unwrap(),
- Mode::VFO => write!(string, ">{:<10}", state.qrg).unwrap(),
+ Mode::BFO => write!(string, " .{:<06} ", disp_freq).unwrap(),
+ Mode::VFO => write!(string, ">.{:<06} ", disp_freq).unwrap(),
}
match state.tune_speed {
@@ -159,7 +167,7 @@ fn main() -> ! {
mode : Mode::VFO,
filter_shift : FilterShift::USB,
bfo_tune_fail : false,
- qrg : 28_000_000,
+ vhf_qrg : VHF_BAND_EDGE,
tune_speed : TuneSpeed::Mid,
transmit : false,
};
@@ -293,7 +301,7 @@ fn main() -> ! {
match state.mode {
Mode::VFO => {
- state.qrg = (state.qrg as i32 + delta * state.vfo_incr()) as u32;
+ state.vhf_qrg = (state.vhf_qrg as i32 + delta * state.vfo_incr()) as u32;
},
Mode::BFO => {
let new_bfo = (state.bfo() as i32 + delta * state.bfo_incr()) as u32;
diff --git a/sw/picardy/src/si_clock.rs b/sw/picardy/src/si_clock.rs
index b304461..8ebf702 100644
--- a/sw/picardy/src/si_clock.rs
+++ b/sw/picardy/src/si_clock.rs
@@ -101,18 +101,9 @@ impl<I2C, E> SiClock<I2C>
siclock.init(si5351::CrystalLoad::_10).unwrap();
// See freqplan.py for Si5351 frequency plan
- // CLK1 = 116MHz
+ // CLK1 unused
siclock.setup_pll_int(si5351::PLL::A, 32).unwrap();
- {
- let clk1 = 116_000_000;
- let (a, b, c) = clock_settings_for_pll(clk1, PLL_A_MULT * REF_CLOCK);
- siclock.setup_multisynth(si5351::Multisynth::MS1, a, b, c, si5351::OutputDivider::Div1).unwrap();
- siclock.select_clock_pll(si5351::ClockOutput::Clk1, si5351::PLL::A);
- siclock.set_clock_enabled(si5351::ClockOutput::Clk1, true);
- siclock.flush_clock_control(si5351::ClockOutput::Clk1).unwrap();
- }
-
set_bfo(&mut siclock, bfo).unwrap();
siclock.reset_pll(si5351::PLL::A).unwrap();