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`timescale 1ns/1ns
module blinky_tb;
reg clk;
reg btn;
initial begin
$dumpfile("blinky_tb.vcd");
$dumpvars(0,blinky_tb);
// $monitor("Time = %0t clk = %0d sig = %0d", $time, clk, sig);
clk = 0;
btn = 1;
#10 btn = 0;
#20 $finish;
end
wire led1;
wire led2;
wire led3;
wire led4;
wire led5;
wire led6;
wire led7;
wire led8;
wire lcol1;
wire lcol2;
wire lcol3;
wire lcol4;
blinky blinky_1 (clk, btn, led1, led2, led3, led4, led5, led6, led7, led8, lcol1, lcol2, lcol3, lcol4);
always #1 clk = ~clk;
endmodule
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