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| author | Matthias P. Braendli <matthias.braendli@mpb.li> | 2019-11-17 17:23:44 +0100 |
|---|---|---|
| committer | Matthias P. Braendli <matthias.braendli@mpb.li> | 2019-11-17 17:24:03 +0100 |
| commit | 4d73f95698a6d0c0ea17736b20b22ea23a1a6474 (patch) | |
| tree | 06ff1b3a57f852a2e8494266c0963b7addb27c79 /sw/ltc2400.cpp | |
| parent | d97e0e51835fdcf0d69708ab46574283643a18d5 (diff) | |
| download | glutte-batteries-4d73f95698a6d0c0ea17736b20b22ea23a1a6474.tar.gz glutte-batteries-4d73f95698a6d0c0ea17736b20b22ea23a1a6474.tar.bz2 glutte-batteries-4d73f95698a6d0c0ea17736b20b22ea23a1a6474.zip | |
Fix interval calculation
Diffstat (limited to 'sw/ltc2400.cpp')
| -rw-r--r-- | sw/ltc2400.cpp | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/sw/ltc2400.cpp b/sw/ltc2400.cpp index 2a76d87..169b7bd 100644 --- a/sw/ltc2400.cpp +++ b/sw/ltc2400.cpp @@ -86,10 +86,10 @@ void ltc2400_init() { cli(); - // Set bit order=MSB first (DORD=0) - // And SPI mode=0 (CPOL=0, CPHA=0) - SPCR &= ~(_BV(DORD) | _BV(CPOL) | _BV(CPHA)); - + // Set SPI Enable and Master mode, + // bit order=MSB first (DORD=0), + // SPI mode=0 (CPOL=0, CPHA=0) + // // clock divider: // SPR1 and SPR0 are the two LSB bits in SPCR // SPR1 SPR0 ~SPI2X Freq @@ -102,11 +102,10 @@ void ltc2400_init() // 0 1 1 fosc/16 // 1 0 1 fosc/64 // 1 1 1 fosc/128 - - constexpr uint8_t SPI_CLOCK_MASK = 0x03; // SPR1 = bit 1, SPR0 = bit 0 on SPCR - constexpr uint8_t SPI_2XCLOCK_MASK = 0x01; // SPI2X = bit 0 on SPSR - SPCR = (SPCR & ~SPI_CLOCK_MASK) | (SPR1 & SPI_CLOCK_MASK); - SPSR = (SPSR & ~SPI_2XCLOCK_MASK); // clear SPI2X + // + // Set SPR1 for /32 + SPCR = _BV(SPE) | _BV(MSTR) | _BV(SPR1); + SPSR = 0; // clear SPI2X sei(); } |