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authorMatthias P. Braendli <matthias.braendli@mpb.li>2018-05-09 17:16:28 +0200
committerMatthias P. Braendli <matthias.braendli@mpb.li>2018-05-09 17:16:28 +0200
commitf6d73ae3ee5f2af8e865bda2e1dbcd6132e7c9c8 (patch)
tree67128fc3e9940e8dd771e475fedacad83da8d685
parent9ef3824a541ab3a052362cf2b4cb108c8974e8fa (diff)
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Document CIC equaliser better
-rw-r--r--doc/example.ini5
1 files changed, 3 insertions, 2 deletions
diff --git a/doc/example.ini b/doc/example.ini
index ae5ed46..a4bfb4a 100644
--- a/doc/example.ini
+++ b/doc/example.ini
@@ -106,9 +106,10 @@ digital_gain=0.8
rate=2048000
; (DEPRECATED) CIC equaliser for USRP1 and USRP2
+; These USRPs have an upsampler in FPGA that does not have a flat frequency
+; response. The CIC equaliser compensates this. This setting is specific to
+; the USRP1 and USRP2 devices.
; Set to 0 to disable CicEqualiser
-; when set to 400000000, an additional USRP2 check is enabled.
-; See DabModulator.cpp line 186
;dac_clk_rate=0
; The USRP1 does not have flexible clocking, you will need