| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Connect ATTiny and PLL differently | Matthias P. Braendli | 2022-04-09 | 2 | -2614/+1042 |
| * | Place and route | Matthias P. Braendli | 2022-04-08 | 5 | -35/+20634 |
| * | Annotate | Matthias P. Braendli | 2022-04-08 | 1 | -16/+16 |
| * | Assign footprints | Matthias P. Braendli | 2022-04-08 | 2 | -428/+462 |
| * | Start schematic | Matthias P. Braendli | 2022-04-08 | 8 | -0/+4611 |
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index : ADF4002_27MHz_PLL | |
| A PLL around the ADF4002 to generate 27MHz from a 10MHz ref |
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