FPGA4U U-Blox Clock Drift Measurement


Measure the drift of the FPGA4U oscillator using a U-Blox LEA-6T reference.


The U-Blox LEA-6T is configured to output a 100kHz signal on TIMEPULSE2. This TIMEPULSE2 signal is fed to a Nios2 system running on the FPGA4U, it is called refclk. On the FPGA4U, the 50MHz is divided down to 100kHz, which is called sysclk.

Both clocks are used by a counter that increments for each refclk rising edge, and decrements for each sysclk rising edge. If both clocks are perfectly in sync, the counter will stay at its initial value, otherwise it will, over time, accumulate the error and represent the drift between the two clocks.

FPGA4U design(Edit)

The Quartus design is available at http://hg.mpb.li/fpga4u-ublox-clk-compensate/

It uses a Qsys designed Nios2 system


Using the U-Center software, the u-blox receiver must be configured to output a 100kHz TIMEPULSE2. These settings are shown in ublox-config.png in the repository.

The two pictures illustrate the wiring between the U-Blox and the LEA-6T.


Over half an hour, the accumulated error represented by the counter value is slightly less than 1800. The value being positive, it means that the GPS refclk is faster than the oscillator on the FPGA4U. If it were exactly 1800, it would represent a 1Hz error on the 100kHz clock, which would imply 240Hz error on 24MHz (10ppm).