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module gpif_wr_tb();
reg sys_clk = 0;
reg sys_rst = 1;
reg gpif_clk = 0;
reg gpif_rst = 1;
reg [15:0] gpif_data;
reg WR = 0, EP = 0;
wire CF, DF;
wire gpif_full_d, gpif_full_c;
wire [18:0] data_o, ctrl_o;
wire src_rdy, dst_rdy;
wire ctrl_src_rdy, ctrl_dst_rdy;
assign ctrl_dst_rdy = 1;
assign dst_rdy = 1;
initial $dumpfile("gpif_wr_tb.vcd");
initial $dumpvars(0,gpif_wr_tb);
initial #1000 gpif_rst = 0;
initial #1000 sys_rst = 0;
always #64 gpif_clk <= ~gpif_clk;
always #47.9 sys_clk <= ~sys_clk;
gpif_wr gpif_write
(.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
.gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP),
.gpif_full_d(DF), .gpif_full_c(CF),
.sys_clk(sys_clk), .sys_rst(sys_rst),
.data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy),
.ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) );
always @(posedge sys_clk)
if(ctrl_src_rdy & ctrl_dst_rdy)
$display("CTRL: %x",ctrl_o);
always @(posedge sys_clk)
if(src_rdy & dst_rdy)
begin
if(data_o[16])
$display("<-------- DATA SOF--------->");
$display("DATA: %x",data_o);
if(data_o[17])
$display("<-------- DATA EOF--------->");
end
initial
begin
#10000;
repeat (1)
begin
WR <= 1;
gpif_data <= 150; // Length
@(posedge gpif_clk);
gpif_data <= 16'h00;
@(posedge gpif_clk);
repeat(254)
begin
gpif_data <= gpif_data + 1;
@(posedge gpif_clk);
end
WR <= 0;
repeat (20)
@(posedge gpif_clk);
WR <= 1;
gpif_data <= 16'hFF;
@(posedge gpif_clk);
repeat(254)
begin
gpif_data <= gpif_data - 1;
@(posedge gpif_clk);
end
end
end // initial begin
initial #100000 $finish;
endmodule // gpif_wr_tb
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