1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module dbsm
(input clk,
input reset,
input clear,
output write_ok,
output write_ptr,
input write_done,
output read_ok,
output read_ptr,
input read_done,
output access_ok,
output access_ptr,
input access_done,
input access_skip_read
);
localparam PORT_WAIT_0 = 0;
localparam PORT_USE_0 = 1;
localparam PORT_WAIT_1 = 2;
localparam PORT_USE_1 = 3;
reg [1:0] write_port_state, access_port_state, read_port_state;
localparam BUFF_WRITABLE = 0;
localparam BUFF_ACCESSIBLE = 1;
localparam BUFF_READABLE = 2;
localparam BUFF_ERROR = 3;
wire [1:0] buff_state[0:1];
always @(posedge clk)
if(reset | clear)
write_port_state <= PORT_WAIT_0;
else
case(write_port_state)
PORT_WAIT_0 :
if(buff_state[0]==BUFF_WRITABLE)
write_port_state <= PORT_USE_0;
PORT_USE_0 :
if(write_done)
write_port_state <= PORT_WAIT_1;
PORT_WAIT_1 :
if(buff_state[1]==BUFF_WRITABLE)
write_port_state <= PORT_USE_1;
PORT_USE_1 :
if(write_done)
write_port_state <= PORT_WAIT_0;
endcase // case (write_port_state)
assign write_ok = (write_port_state == PORT_USE_0) | (write_port_state == PORT_USE_1);
assign write_ptr = (write_port_state == PORT_USE_1);
always @(posedge clk)
if(reset | clear)
access_port_state <= PORT_WAIT_0;
else
case(access_port_state)
PORT_WAIT_0 :
if(buff_state[0]==BUFF_ACCESSIBLE)
access_port_state <= PORT_USE_0;
PORT_USE_0 :
if(access_done)
access_port_state <= PORT_WAIT_1;
PORT_WAIT_1 :
if(buff_state[1]==BUFF_ACCESSIBLE)
access_port_state <= PORT_USE_1;
PORT_USE_1 :
if(access_done)
access_port_state <= PORT_WAIT_0;
endcase // case (access_port_state)
assign access_ok = (access_port_state == PORT_USE_0) | (access_port_state == PORT_USE_1);
assign access_ptr = (access_port_state == PORT_USE_1);
always @(posedge clk)
if(reset | clear)
read_port_state <= PORT_WAIT_0;
else
case(read_port_state)
PORT_WAIT_0 :
if(buff_state[0]==BUFF_READABLE)
read_port_state <= PORT_USE_0;
PORT_USE_0 :
if(read_done)
read_port_state <= PORT_WAIT_1;
PORT_WAIT_1 :
if(buff_state[1]==BUFF_READABLE)
read_port_state <= PORT_USE_1;
PORT_USE_1 :
if(read_done)
read_port_state <= PORT_WAIT_0;
endcase // case (read_port_state)
assign read_ok = (read_port_state == PORT_USE_0) | (read_port_state == PORT_USE_1);
assign read_ptr = (read_port_state == PORT_USE_1);
buff_sm #(.PORT_USE_FLAG(PORT_USE_0)) buff0_sm
(.clk(clk), .reset(reset), .clear(clear),
.write_done(write_done), .access_done(access_done), .access_skip_read(access_skip_read), .read_done(read_done),
.write_port_state(write_port_state), .access_port_state(access_port_state), .read_port_state(read_port_state),
.buff_state(buff_state[0]));
buff_sm #(.PORT_USE_FLAG(PORT_USE_1)) buff1_sm
(.clk(clk), .reset(reset), .clear(clear),
.write_done(write_done), .access_done(access_done), .access_skip_read(access_skip_read), .read_done(read_done),
.write_port_state(write_port_state), .access_port_state(access_port_state), .read_port_state(read_port_state),
.buff_state(buff_state[1]));
endmodule // dbsm
module buff_sm
#(parameter PORT_USE_FLAG=0)
(input clk, input reset, input clear,
input write_done, input access_done, input access_skip_read, input read_done,
input [1:0] write_port_state, input [1:0] access_port_state, input [1:0] read_port_state,
output reg [1:0] buff_state);
localparam BUFF_WRITABLE = 0;
localparam BUFF_ACCESSIBLE = 1;
localparam BUFF_READABLE = 2;
localparam BUFF_ERROR = 3;
always @(posedge clk)
if(reset | clear)
buff_state <= BUFF_WRITABLE;
else
case(buff_state)
BUFF_WRITABLE :
if(write_done & (write_port_state == PORT_USE_FLAG))
buff_state <= BUFF_ACCESSIBLE;
BUFF_ACCESSIBLE :
if(access_done & (access_port_state == PORT_USE_FLAG))
if(access_skip_read)
buff_state <= BUFF_WRITABLE;
else
buff_state <= BUFF_READABLE;
BUFF_READABLE :
if(read_done & (read_port_state == PORT_USE_FLAG))
buff_state <= BUFF_WRITABLE;
BUFF_ERROR :
;
endcase
endmodule // buff_sm
|
