1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
|
//
// Copyright 2010 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
#include "usrp1_impl.hpp"
#include "fpga_regs_standard.h"
#include <uhd/usrp/dsp_utils.hpp>
#include <uhd/usrp/dsp_props.hpp>
#include <boost/bind.hpp>
#include <boost/format.hpp>
#include <iostream>
#include <cmath>
using namespace uhd;
using namespace uhd::usrp;
/***********************************************************************
* RX DDC Initialization
**********************************************************************/
void usrp1_impl::rx_dsp_init(void)
{
_rx_dsp_proxy = wax_obj_proxy::make(
boost::bind(&usrp1_impl::rx_dsp_get, this, _1, _2),
boost::bind(&usrp1_impl::rx_dsp_set, this, _1, _2));
rx_dsp_set(DSP_PROP_HOST_RATE, _clock_ctrl->get_master_clock_freq() / 16);
}
/***********************************************************************
* RX DDC Get
**********************************************************************/
void usrp1_impl::rx_dsp_get(const wax::obj &key, wax::obj &val)
{
switch(key.as<dsp_prop_t>()){
case DSP_PROP_NAME:
val = std::string("usrp1 ddc0");
return;
case DSP_PROP_OTHERS:
val = prop_names_t();
return;
case DSP_PROP_FREQ_SHIFT:
val = _rx_dsp_freq;
return;
case DSP_PROP_CODEC_RATE:
val = _clock_ctrl->get_master_clock_freq();
return;
case DSP_PROP_HOST_RATE:
val = _clock_ctrl->get_master_clock_freq()/_rx_dsp_decim;
return;
default: UHD_THROW_PROP_GET_ERROR();
}
}
/***********************************************************************
* RX DDC Set
**********************************************************************/
void usrp1_impl::rx_dsp_set(const wax::obj &key, const wax::obj &val)
{
switch(key.as<dsp_prop_t>()) {
case DSP_PROP_FREQ_SHIFT: {
double new_freq = val.as<double>();
_iface->poke32(FR_RX_FREQ_0,
-dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_master_clock_freq()));
_tx_dsp_freq = new_freq;
return;
}
case DSP_PROP_HOST_RATE: {
//FIXME: Stop and resume streaming during set?
unsigned int rate =
_clock_ctrl->get_master_clock_freq() / val.as<double>();
if ((rate & 0x01) || (rate < 4) || (rate > 256)) {
std::cerr << "Decimation must be even and between 4 and 256"
<< std::endl;
return;
}
_rx_dsp_decim = rate;
_rx_samps_per_poll_interval = 0.1 * _clock_ctrl->get_master_clock_freq() / rate;
_iface->poke32(FR_DECIM_RATE, _rx_dsp_decim/2 - 1);
}
return;
default: UHD_THROW_PROP_SET_ERROR();
}
}
/***********************************************************************
* TX DUC Initialization
**********************************************************************/
void usrp1_impl::tx_dsp_init(void)
{
_tx_dsp_proxy = wax_obj_proxy::make(
boost::bind(&usrp1_impl::tx_dsp_get, this, _1, _2),
boost::bind(&usrp1_impl::tx_dsp_set, this, _1, _2));
//initial config and update
tx_dsp_set(DSP_PROP_HOST_RATE, _clock_ctrl->get_master_clock_freq() * 2 / 16);
}
/***********************************************************************
* TX DUC Get
**********************************************************************/
void usrp1_impl::tx_dsp_get(const wax::obj &key, wax::obj &val)
{
switch(key.as<dsp_prop_t>()) {
case DSP_PROP_NAME:
val = std::string("usrp1 duc0");
return;
case DSP_PROP_OTHERS:
val = prop_names_t(); //empty
return;
case DSP_PROP_FREQ_SHIFT:
val = _tx_dsp_freq;
return;
case DSP_PROP_CODEC_RATE:
val = _clock_ctrl->get_master_clock_freq() * 2;
return;
case DSP_PROP_HOST_RATE:
val = _clock_ctrl->get_master_clock_freq() * 2 / _tx_dsp_interp;
return;
default: UHD_THROW_PROP_GET_ERROR();
}
}
/***********************************************************************
* TX DUC Set
**********************************************************************/
void usrp1_impl::tx_dsp_set(const wax::obj &key, const wax::obj &val)
{
switch(key.as<dsp_prop_t>()) {
// TODO: Set both codec frequencies until we have duality properties
case DSP_PROP_FREQ_SHIFT: {
double new_freq = val.as<double>();
_codec_ctrls[DBOARD_SLOT_A]->set_duc_freq(new_freq);
_codec_ctrls[DBOARD_SLOT_B]->set_duc_freq(new_freq);
_tx_dsp_freq = new_freq;
return;
}
case DSP_PROP_HOST_RATE: {
unsigned int rate =
_clock_ctrl->get_master_clock_freq() * 2 / val.as<double>();
if ((rate & 0x01) || (rate < 8) || (rate > 512)) {
std::cerr << "Interpolation rate must be even and between 8 and 512"
<< std::endl;
return;
}
_tx_dsp_interp = rate;
_tx_samps_per_poll_interval = 0.1 * _clock_ctrl->get_master_clock_freq() * 2 / rate;
_iface->poke32(FR_INTERP_RATE, _tx_dsp_interp / 4 - 1);
return;
}
default: UHD_THROW_PROP_SET_ERROR();
}
}
|
