blob: 1b0d7b7192e1221f1450a8c41b84e4314df8d4de (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
|
========================================================================
UHD - USRP-B2x0 Series Device Manual
========================================================================
.. contents:: Table of Contents
------------------------------------------------------------------------
Comparative features list - B200
------------------------------------------------------------------------
**Hardware Capabilities:**
* Integrated RF frontend (70 MHz - 6 GHz)
* External PPS reference input
* External 10 MHz reference input
* Configurable clock rate
* Internal GPSDO option
* B210 Only:
* MICTOR Debug Connector
* JTAG Connector
**FPGA Capabilities:**
* Timed commands in FPGA
* Timed sampling in FPGA
------------------------------------------------------------------------
Specify a Non-standard Image
------------------------------------------------------------------------
UHD software will automatically select the USRP B2X0 images from the installed images package.
The image selection can be overridden with the **fpga** and **fw** device address parameters.
Example device address string representations to specify non-standard images:
::
fpga=usrp_b200_fpga.bin
-- OR --
fw=usrp_b200_fw.hex
------------------------------------------------------------------------
Changing the Master Clock Rate
------------------------------------------------------------------------
The master clock rate feeds the RF frontends and the DSP chains.
Users may select non-default clock rates to acheive integer decimations or interpolations in the DSP chains.
The default master clock rate defaults to 32 MHz, but can be set to any rate between 5 MHz and 61.44 MHz.
The user can set the master clock rate through the usrp API call set_master_clock_rate(),
or the clock rate can be set through the device arguments, which many applications take:
::
uhd_usrp_probe --args="master_clock_rate=52e6"
------------------------------------------------------------------------
RF Frontend Notes
------------------------------------------------------------------------
The B200 features and integrated RF frontend.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Frontend tuning
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The RF frontend has individually tunable receive and transmit chains.
On the B200, there is one transmit and one receive RF frontend.
On the B210, both transmit and receive can be used in a MIMO configuration.
For the MIMO case, both receive frontends share the RX LO,
and both transmit frontends share the TX LO.
Each LO is tunable between 50 MHz and 6 GHz.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Frontend gain
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
All frontends have individual analog gain controls.
The receive frontends have 73 dB of available gain;
and the transmit frontends have 89.5 dB of available gain.
Gain settings are application specific,
but it is recommended that users consider using at least
half of the available gain to get reasonable dynamic range.
------------------------------------------------------------------------
Hardware Reference
------------------------------------------------------------------------
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
LED Indicators
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Below is a table of the LED indicators and their meanings:
=============== ======================== ========================================================
Component ID Description Details
=============== ======================== ========================================================
LED600 Power Indicator | off = no power applied
| red = power applied (external or USB)
LED800 Channel 2 RX2 Activity | off = no activity
| green = receiving
LED801 Channel 2 TX/RX Activity | off = no activity
| green = receiving
| red = transmitting
| orange = switching between transmitting and receiving
LED802 Channel 1 TX/RX Activity | off = no activity
| green = receiving
| red = transmitting
| orange = switching between transmitting and receiving
LED803 Channel 1 RX2 Activity | off = no activity
| green = receiving
LED100 GPS lock indicator | off = no lock
| green = lock
=============== ======================== ========================================================
TX LED indicators are on when transimitting data and off when no samples are available to transmit. RX LED indicators are on when sending samples to the host and off when unable to do so. This means that TX/RX activity LED indicators will blink off in a temporary transmit underflow or receive overflow condition, indicating that the host is not sending or receiving samples fast enough. The host will be notified of the condition and output a "U" or "O" as well.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
External Connections
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Below is a table showing the external connections and respective power information:
=============== ======================== ========================================================
Component ID Description Details
=============== ======================== ========================================================
J601 External Power | 6 V
| 3 A
J701 USB Connector | USB 3.0
J104 External PPS Input | 1.8 V - 5 V
J101 GPS Antenna | GPSDO will supply nominal voltage to antenna.
J100 External 10 MHz Input | +15 dBm max
J800 RF B: TX/RX | TX power +20dBm max
| RX power -15dBm max
J802 RF B: RX2 | RX power -15dBm max
J803 RF A: RX2 | RX power -15dBm max
J801 RF A: TX/RX | TX power +20dBm max
| RX power -15dBm max
=============== ======================== ========================================================
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
On-Board Connectors and Switches
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Below is a table showing the on-board connectors and switches:
=============== ======================== ========================================================
Component ID Description Details
=============== ======================== ========================================================
J502* Mictor Connector | Interface to FPGA for I/O and inspection.
J503* JTAG Header | Interface to FPGA for programming and debugging.
J400 Debug Header | Pin 1 - serial data out (115200 8,N,1 @ 1.8V)
| Pin 2 - ground
| Pin 3 - serial data in (not connected)
S100 GPSDO ISP Enable Switch | Not supported
S700 FX3 Hard Reset Switch
=============== ======================== ========================================================
\* B210 Only
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Test Points
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Below is a table showing the test points:
=============== ================================== ===================
Component ID Description Details
=============== ================================== ===================
J603 Upstream Voltage Regulation | 3.3 V supply
Test Point | Pin 1 - 3.7 V
| Pin 2 - gnd
J604 Catalina Supply Test Point | Pin 1 - 1.3 V
| Pin 2 - gnd
J605 FPGA Supply Test Point | Pin 1 - 1.2 V
| Pin 2 - gnd
J606 FX3 Supply Test Point | Pin 1 - 1.2V
| Pin 2 - gnd
J609 Upstream Voltage Regulation | 1.3 V supply
Test Point | Pin 1 - 1.8 V
| Pin 2 - gnd
T600 External Voltage Supply
Test Point
T601 1.3 V Catalina Power Good
Test Point
T602 1.3 V Catalina Synthesizer
Power Good Test Point
TP302 Catalina AUX DAC1 Test Point
TP303 Catalina AUX DAC2 Test Point
T700 Not connected
T701 Not connected
T702 FX3 External Clock In | Not used
T703 FX3 Charger Detect Out
=============== ================================== ===================
|
