blob: 0b23ea8375bb8e573f63c67c5d9a135e3cc21eaa (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
|
/*! \page page_usrp_b100 USRP B100 Series
\tableofcontents
\section b100_features Comparative features list
- Hardware Capabilities:
- 1 transceiver card slot
- External PPS reference input
- External 10 MHz reference input
- Configurable clock rate (defaults 64 MHz)
- FPGA Capabilities:
- 1 RX DDC chain in FPGA
- 1 TX DUC chain in FPGA
- Timed commands in FPGA
- Timed sampling in FPGA
- sc8 and sc16 sample modes
- Up to 8 MHz of RF BW with 16-bit samples
- Up to 16 MHz of RF BW with 8-bit samples
\section b100_imgs Specify a Non-standard Image
UHD software will automatically select the USRP B100 images from the
installed images package. The image selection can be overridden with the
`--fpga=` and `--fw=` device address parameters.
Example device address string representations to specify non-standard
images:
fpga=usrp_b100_fpga_2rx.bin
-- OR --
fw=usrp_b100_fw.ihx
\section b100_mcr Changing the Master Clock Rate
The master clock rate of the B100 feeds both the FPGA DSP and the codec
chip. Hundreds of rates between 32 MHz and 64 MHz are available. A few
notable rates are:
- **64 MHz:** maximum rate of the codec chip
- **61.44 MHz:** good for UMTS/WCDMA applications
- **52 MHz:** good for GSM applications
\subsection b100_mcr_vcxo Set 61.44 MHz - uses external VCXO
To use the 61.44 MHz clock rate, the USRP embedded will require one
jumper to be moved, and X4 must be populated with a 61.44 MHz
oscillator.
- **J15** is a three pin header, move the jumper to (pin1, pin2)
- **357LB3I061M4400** is the recommended oscillator for X4
<b>Note:</b> See instructions below to communicate the desired clock rate
into UHD software.
\subsection b100_mcr_vco Set other rates - uses internal VCO
To use other clock rates, the jumper will need to be in the default
position.
- **J15** is a three pin header, move the jumper to (pin2, pin3)
To communicate the desired clock rate into UHD software, specify the
special device address argument, where the key is
`master_clock_rate` and the value is a rate in Hz. Example:
uhd_usrp_probe --args="master_clock_rate=52e6"
\section b100_hw Hardware setup notes
\subsection b100_hw_leds Front panel LEDs
The LEDs on the front panel can be useful in debugging hardware and
software issues. The LEDs reveal the following about the state of the
device:
- **LED A:** transmitting
- **LED B:** FPGA loaded
- **LED C:** receiving
- **LED D:** FPGA loaded
- **LED E:** reference lock
- **LED F:** board power
\section b100_misc Miscellaneous
\subsection b100_misc_sensors Available Sensors
The following sensors are available; they can be queried through the
API.
- **ref_locked:** clock reference locked (internal/external)
\subsection b100_known_issues Known Issues
- When using a TVRX2, you will need to send the tune command twice on the first
tune.
*/
// vim:ft=doxygen:
|
