summaryrefslogtreecommitdiffstats
path: root/control_lib/WB_SIM.sav
blob: 467cd35ef2301e194236796497dcee7848c96c5a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
[size] 1400 971
[pos] -1 -1
*-6.099828 350 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
@28
wb_sim.wb_rst
wb_sim.wb_clk
@23
wb_sim.rom_data[47:0]
@22
wb_sim.rom_addr[15:0]
@28
wb_sim.start
wb_sim.wb_ack
@22
wb_sim.wb_adr[15:0]
@28
wb_sim.wb_cyc
@22
wb_sim.wb_dat[31:0]
wb_sim.wb_sel[3:0]
@28
wb_sim.wb_stb
wb_sim.wb_we
@22
wb_sim.port_output[31:0]
@28
wb_sim.system_control.POR
wb_sim.system_control.aux_clk
wb_sim.system_control.clk_fpga
@29
wb_sim.system_control.done
@28
wb_sim.system_control.dsp_clk
wb_sim.system_control.fin_del1
wb_sim.system_control.fin_del2
wb_sim.system_control.fin_del3
wb_sim.system_control.fin_ret_aux
@29
wb_sim.system_control.fin_ret_fpga
@28
wb_sim.system_control.finished
wb_sim.system_control.reset_out
wb_sim.system_control.start
wb_sim.system_control.started
wb_sim.system_control.wb_clk_o
wb_sim.system_control.wb_rst_o
wb_sim.system_control.wb_rst_o_alt