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[size] 1400 971
[pos] -1 -1
*-11.026821 2450 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
@28
system_control_tb.aux_clk
@29
system_control_tb.clk_fpga
@28
system_control_tb.dsp_clk
system_control_tb.dsp_rst
system_control_tb.proc_rst
system_control_tb.rl_done
system_control_tb.rl_rst
system_control_tb.wb_clk
system_control_tb.wb_rst
system_control_tb.system_control.POR
@22
system_control_tb.system_control.POR_ctr[3:0]
@28
system_control_tb.clock_ready
system_control_tb.system_control.half_clk
system_control_tb.system_control.fin_ret_half
system_control_tb.system_control.fin_ret_aux
system_control_tb.system_control.gate_dsp_clk
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