NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;

NET "IFCLK" TNM_NET = "IFCLK";
TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %;

#constrain FX2 IO
NET "GPIF_D<*>" MAXDELAY = 5.5 ns;
NET "GPIF_CTL<*>" MAXDELAY = 5.5 ns;
NET "GPIF_ADR<*>" MAXDELAY = 5.5ns;
NET "GPIF_SLWR" MAXDELAY = 5.5 ns;
NET "GPIF_SLRD" MAXDELAY = 5.5 ns;
NET "GPIF_SLOE" MAXDELAY = 5.5 ns;
NET "GPIF_PKTEND" MAXDELAY = 5.5 ns;