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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
fifo_xlnx_32x36_2clk YourInstanceName (
	.rst(rst),
	.wr_clk(wr_clk),
	.rd_clk(rd_clk),
	.din(din), // Bus [35 : 0] 
	.wr_en(wr_en),
	.rd_en(rd_en),
	.dout(dout), // Bus [35 : 0] 
	.full(full),
	.almost_full(almost_full),
	.empty(empty),
	.prog_full(prog_full));

// INST_TAG_END ------ End INSTANTIATION Template ---------