/*! \page page_usrp_b200 USRP B2x0 Series

\tableofcontents

\section b200_features Comparative features list - B200/B210

- Hardware Capabilities:
    -   Integrated RF frontend (70 MHz - 6 GHz)
    -   External PPS reference input
    -   External 10 MHz reference input
    -   Configurable clock rate
    -   Variable analog bandwidth (200 kHz - 56 MHz)
    -   Internal GPSDO option (see \subpage page_gpsdo_b2x0 for details)
    -   B210 Only:
        -   MICTOR Debug Connector
        -   JTAG Connector
    -   Revision 6 with GPIO header
- FPGA Capabilities:
    -   Timed commands in FPGA
    -   Timed sampling in FPGA

\section b200_imgs Specify a Non-standard Image

UHD software will automatically select the USRP B2X0 images from the
installed images package. The image selection can be overridden with the
`fpga` and `fw` device address parameters.

Example device address string representations to specify non-standard
images:

    fpga=usrp_b200_fpga.bin

    -- OR --

    fw=usrp_b200_fw.hex

\section b200_mcr Changing the Master Clock Rate

The master clock rate feeds the RF frontends and the DSP chains. Users
may select non-default clock rates to acheive integer decimations or
interpolations in the DSP chains. The clock rate can be set to any value
between 5 MHz and 61.44 MHz (or 30.72 MHz for dual-channel mode).
Note that rates above 56 MHz are possible, but not recommended.

The user can set the master clock rate through the usrp API call
uhd::usrp::multi_usrp::set_master_clock_rate(), or the clock rate can be set through the
device arguments, which many applications take:

    uhd_usrp_probe --args="master_clock_rate=52e6"

The property to control the master clock rate is a double value, called `tick_rate`.

\subsection b200_auto_mcr Automatic Clock Rate Setting

The default clock rate setting is to automatically set a clock rate
depending on the requested sampling rate. The automatic clock rate selection
is disabled when either `master_clock_rate` is given in the device initialization
arguments, or when uhd::usrp::multi_usrp::set_master_clock_rate() is called.

Note that the master clock rate must be an integer multiple of the sampling
rate. If a master clock rate is chosen for which this condition does not
hold, a warning will be displayed and a different sampling rate is used internally.

Nevertheless, there are multiple valid values for the master clock rate
for most sampling rates. The auto clock rate selection attempts to use
the largest possible clock rate as to enable as many half-band filters
as possible. Expert users might have cases where a more fine-grained
control over the resampling stages is required, in which case manually
selecting a master clock rate might be more suitable than the automatic
rate.

The property to dis- or enable the auto tick rate is a boolean value,
`auto_tick_rate`.

\section b200_fe RF Frontend Notes

The B200 features an integrated RF frontend.

\subsection b200_fe_tuning Frontend tuning

The RF frontend has individually tunable receive and transmit chains. On
the B200, there is one transmit and one receive RF frontend. On the
B210, both transmit and receive can be used in a MIMO configuration. For
the MIMO case, both receive frontends share the RX LO, and both transmit
frontends share the TX LO. Each LO is tunable between 50 MHz and 6 GHz.

\subsection b200_fe_gain Frontend gain

All frontends have individual analog gain controls. The receive
frontends have 73 dB of available gain; and the transmit frontends have
89.5 dB of available gain. Gain settings are application specific, but
it is recommended that users consider using at least half of the
available gain to get reasonable dynamic range.

\subsection b200_fe_bw Frontend bandwidth

The analog frontend has a seamlessly adjustable bandwidth of 200 kHz to 56 MHz.

Generally, when requesting any possible master clock rate, UHD will
automatically configure the analog filters to avoid any aliasing (RX) or
out-of-band emissions whilst letting through the cleanest possible signal.

If you, however, happen to have a very strong interferer within half the master
clock rate of your RX LO frequency, you might want to reduce this analog
bandwidth.  You can do so by calling
uhd::usrp::multi_usrp::set_rx_bandwidth(bw).

The property to control the analog RX bandwidth is `bandwidth/value`.

UHD will not allow you to set bandwidths larger than your current master clock
rate.

\section Hardware Reference

\subsection LED Indicators

Below is a table of the LED indicators and their meanings:

<table>
  <tr>
    <th>Component ID</th><th>Description</th><th>Details</th>
  </tr>
  <tr>
    <td>LED600</td> <td>Power Indicator</td> <td>off = no power applied<br>
                                                 red = power applied (external or USB)</td>
  </tr>
  <tr>
    <td>LED800</td> <td>Channel 2 RX2 Activity</td> <td>off = no power applied<br>
                                                        green = receiving</td>
  </tr>
  <tr>
    <td>LED801</td> <td>Channel 2 TX/RX Activity</td> <td>off = no activity<br>
                                                          green = receiving<br>
                                                          red = transmitting<br>
                                                          orange = switching between transmitting and receiving</td>
  </tr>
  <tr>
    <td>LED802</td> <td>Channel 1 TX/RX Activity</td> <td>off = no activity
                                                          green = receiving<br>
                                                          red = transmitting<br>
                                                          orange = switching between transmitting and receiving</td>
  </tr>
  <tr>
    <td>LED803</td> <td>Channel 1 RX2 Activity</td> <td>off = no power applied<br>
                                                        green = receiving</td>
  </tr>
  <tr>
    <td>LED100</td> <td>GPS lock indicator</td> <td>off = no lock<br>
                                                    green = lock</td>
  </tr>
</table>

TX LED indicators are on when transimitting data and off when no samples are
available to transmit.  RX LED indicators are on when sending samples to the
host and off when unable to do so.  This means that TX/RX activity LED
indicators will blink off in a temporary transmit underflow or receive overflow
condition, indicating that the host is not sending or receiving samples fast
enough.  The host will be notified of the condition and output a "U" or "O" as
well.

\subsection External Connections

Below is a table showing the external connections and respective power information:

<table>
<tr>
  <th>Component ID</th> <th>Description</th>            <th> Details</th>
</tr>
<tr>
  <td>J601</td>         <td>External Power</td>         <td>6 V<br>3 A</td>
</tr>
<tr>
  <td>J701</td>         <td>USB Connector</td>          <td>USB 3.0</td>
</tr>
<tr>
  <td>J104</td>         <td>External PPS Input</td>     <td>1.8 V - 5 V</td>
</tr>
<tr>
  <td>J101</td>         <td>GPS Antenna</td>            <td>GPSDO will supply nominal voltage to antenna.</td>
</tr>
<tr>
  <td>J100</td>         <td>External 10 MHz Input</td>  <td>+15 dBm max</td
</tr>
<tr>
  <td>J800</td>         <td>RF B: TX/RX</td>            <td>TX power +20dBm max<br>
                                                            RX power -15dBm max</td>
</tr>
<tr>
  <td>J802</td>         <td>RF B: RX2</td>              <td>RX power -15dBm max</td>
</tr>
<tr>
  <td>J803</td>         <td>RF A: RX2</td>              <td>RX power -15dBm max</td>
</tr>
<tr>
  <td>J801</td>         <td>RF A: TX/RX</td>            <td>TX power +20dBm max<br>
                                                            RX power -15dBm max</td>
</tr>
</table>

\subsection b200_switches On-Board Connectors and Switches

Below is a table showing the on-board connectors and switches:

Component ID            |  Description               | Details
------------------------|----------------------------|---------------------------------------------------
 J502<sup>1</sup>       |  Mictor Connector          | Interface to FPGA for I/O and inspection.
 J503<sup>1</sup>       |  JTAG Header               | Interface to FPGA for programming and debugging.
 J504<sup>2</sup>       |  GPIO Header               | Header running to the FPGA for GPIO purposes.
 S700                   |  FX3 Hard Reset Switch     | Resets the USB controller / System reset
 U100                   |  GPSDO socket              | Interface to GPS disciplined reference oscillator

<sup>1</sup> Only on the B210

<sup>2</sup> Only since rev. 6 (green board)

*/

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