Format: http://dep.debian.net/deps/dep5/ Upstream-Name: UHD Upstream-Contact: http://www.ettus.com/contact Source: https://github.com/EttusResearch/uhd X-Note: The upstream package source tarball was generated from the tag: git archive --format=tar --prefix=uhd-3.7.3/ release_003_007_003 | xz > ../uhd_3.7.3.orig.tar.gz Comment: Only the host directory of the distributed source is used to build the uhd-host package for Debian main. Copyright: Copyright 2010-2018 Ettus Research, A National Instruments Company License: GPL-3+ Files: * Copyright: Copyright 2010-2018 Ettus Research, A National Instruments Company License: GPL-3+ Files: host/lib/rpclib/* Copyright: Copyright (c) 2015-2017, Tamás Szelei License: MIT Files: images/* firmware/fx2/b100/CMakeLists.txt firmware/fx2/CMakeLists.txt firmware/fx2/config/CMakeASM_SDCCInformation.cmake firmware/fx2/config/Rename.cmake firmware/fx2/config/Toolchain-sdcc.cmake firmware/fx2/usrp1/CMakeLists.txt firmware/fx3/* firmware/octoclock/* firmware/x300/* firmware/README.txt Copyright: Copyright 2010-2018 Ettus Research, A National Instruments Company License: GPL-3+ Comment: Not used for uhd-host package Files: debian/* Copyright: © 2011-2012 A. Maitland Bottoms License: GPL-3+ Files: host/cmake/Modules/FindGit.cmake Copyright: Copyright 2010 Kitware, Inc. License: Kitware-BSD Files: host/cmake/Modules/FindUSB1.cmake Copyright: Copyright (c) 2006, 2008 Laurent Montel, License: Kitware-BSD Files: firmware/fx2/* Copyright: 2003,2004,2006,2007 Free Software Foundation, Inc. License: GPL-3+ Files: firmware/fx2/config/CMakeTestASM_SDCCCompiler.cmake firmware/fx2/config/CMakeDetermineASM_SDCCCompiler.cmake Copyright: 2008-2009 Kitware, Inc. License: Kitware-BSD Comment: Not used for uhd-host package Files: firmware/zpu/apps* firmware/zpu/bin/* firmware/zpu/lib/* firmware/zpu/lwip/*.h firmware/zpu/usrp2/* Copyright: Copyright 2007-2009 Free Software Foundation, Inc. License: GPL-3+ Comment: Not used for uhd-host package Files: firmware/zpu/lwip/lwip-1.3.1 Copyright: (c) 2001-2004 Swedish Institute of Computer Science. License: lwip-BSD Comment: liIP Author Adam Dunkels http://savannah.nongnu.org/projects/lwip/ Also includes other BSD licensed code from additional copyright holders outlined in detail below... Files: firmware/zpu/lwip/lwip-1.3.1/src/core/dns.c firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/dns.h Copyright: (c) 2002-2003, Adam Dunkels. License: lwip-BSD Comment: Not used for uhd-host package * Port to lwIP from uIP * by Jim Pettinato April 2007 * ported from uIP resolv.c Files: firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/autoip.c firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/autoip.h Copyright: (c) 2007 Dominik Spies * All rights reserved. License: lwip-BSD Comment: Not used for uhd-host package Files: firmware/zpu/lwip/lwip-1.3.1/src/core/dhcp.c firmware/zpu/lwip/lwip-1.3.1/src/netif/etharp.c firmware/zpu/lwip/lwip-1.3.1/src/include/netif/etharp.h firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp.h Copyright: (c) 2001-2004 Leon Woestenberg License: lwip-BSD Comment: Not used for uhd-host package Files: firmware/zpu/lwip/lwip-1.3.1/src/include/netif/etharp.h firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp.h firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp_asn1.h firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp_msg.h firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp_structs.h firmware/zpu/lwip/lwip-1.3.1/src/core/dhcp.c firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/mib2.c firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/msg_out.c firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/msg_in.c firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/asn1_dec.c firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/asn1_enc.c firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/mib_structs.c firmware/zpu/lwip/lwip-1.3.1/src/netif/etharp.c Copyright: (c) 2001-2004,2006 Axon Digital Design B.V., The Netherlands. License: lwip-BSD Comment: Not used for uhd-host package Christiaan Simons Files: firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pppdebug.h: Copyright: (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. portions Copyright (c) 1998 Global Election Systems Inc. portions Copyright (c) 2001 by Cognizant Pty Ltd. License: MBSI-BSD Comment: Not used for uhd-host package Files: firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/randm.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/randm.h Copyright: (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. Copyright (c) 1998 Global Election Systems Inc. License: MBSI-BSD Comment: Not used for uhd-host package * 03-01-01 Marc Boucher * Ported to lwIP. * 98-06-03 Guy Lancaster , Global Election Systems Inc. * Extracted from avos. Files: firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chpms.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chpms.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chap.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chap.h Copyright: (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. portions Copyright (c) 1998 Global Election Systems Inc. License: MBSI-BSD Comment: Not used for uhd-host package Files: firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/auth.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/auth.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/magic.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/magic.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/fsm.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/fsm.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pap.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pap.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/lcp.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/lcp.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ipcp.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ipcp.h Copyright: (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. portions Copyright (c) 1997,1998 by Global Election Systems Inc. License: MBSI-BSD Comment: Not used for uhd-host package Files: firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chpms.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chpms.h Copyright: (c) 1995 Eric Rosenquist, Strata Software Limited. * All rights reserved. License: Rosenquist Comment: Not used for uhd-host package http://www.strataware.com/ Files: firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chap.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chap.h Copyright: (c) 1991 Gregory M. Christy * All rights reserved. License: Christy Files: firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/auth.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chap.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chap.h Copyright: (c) 1993,1994 The Australian National University. * All rights reserved. License: Australian-National-University Comment: Not used for uhd-host package Files: firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/auth.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/auth.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pap.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pap.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/lcp.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/lcp.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ipcp.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ipcp.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/fsm.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/fsm.h firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/magic.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/magic.h Copyright: (c) 1989 Carnegie Mellon University. * All rights reserved. License: Carnegie-Mellon-University Comment: Not used for uhd-host package Files: firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp_oe.c firmware/zpu/lwip/lwip-1.3.1/src/include/netif/ppp_oe.h Copyright: (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc. License: MBSI-BSD Comment: Not used for uhd-host package Files: firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/igmp.c firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/igmp.h Copyright: (c) 2002 CITEL Technologies Ltd. * All rights reserved. License: CITEL-BSD Comment: Not used for uhd-host package Files: firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp_oe.c firmware/zpu/lwip/lwip-1.3.1/src/include/netif/ppp_oe.h Copyright: (c) 2002 The NetBSD Foundation, Inc. License: NetBSD Comment: Not used for uhd-host package /* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */ * This code is derived from software contributed to The NetBSD Foundation * by Martin Husemann . Files: firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/vj.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/vj.h Copyright: (c) 1989 Regents of the University of California. * All rights reserved. License: VJ-BSD Comment: Not used for uhd-host package * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989: * Initial distribution. * * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au, * so that the entire packet being decompressed doesn't have * to be in contiguous memory (just the compressed header). * * Modified March 1998 by Guy Lancaster, glanca@gesn.com, * for a 16 bit processor. Files: firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/md5.c firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/md5.h Copyright: (C) 1990, RSA Data Security, Inc. All rights reserved. License: RSA-BSD Comment: Not used for uhd-host package ** Files: fpga-src/* Copyright: 2008-2018 Ettus Research, A National Instruments Company License: GPL-3+ Comment: Not used for uhd-host package Files: fpga-src/usrp2/opencores/spi_boot/COPYING fpga-src/usrp1/rbf/rev2/Makefile.am fpga-src/usrp1/rbf/Makefile.am fpga-src/usrp1/rbf/rev4/Makefile.am fpga-src/usrp1/Makefile.am fpga-src/usrp1/gen_makefile_extra.py fpga-src/usrp1/toplevel/mrfm/mrfm_fft.py fpga-src/usrp1/toplevel/mrfm/mrfm.py fpga-src/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v Copyright: Copyright (C) 1989,1991,2004-2007,2009 Free Software Foundation, Inc. License: GPL-3+ Comment: Not used for uhd-host package Files: fpga-src/usrp1/sdr_lib/master_control.v fpga-src/usrp1/sdr_lib/atr_delay.v Copyright: (C) 2007 Corgan Enterprises LLC License: GPL-2+ Comment: Not used for uhd-host package Files: fpga-src/usrp1/sdr_lib/master_control_multi.v fpga-src/usrp1/toplevel/include/common_config_2rx_0tx.vh fpga-src/usrp1/toplevel/include/common_config_2rxhb_0tx.vh fpga-src/usrp1/toplevel/usrp_multi/config.vh fpga-src/usrp1/toplevel/usrp_multi/usrp_multi.v Copyright: (C) 2006 Martin Dudok van Heel License: GPL-2+ Comment: Not used for uhd-host package Files: fpga-src/usrp2/sdr_lib/round_reg.v fpga-src/usrp2/sdr_lib/ddc.v fpga-src/usrp2/sdr_lib/cordic_z24.v fpga-src/usrp2/sdr_lib/duc.v fpga-src/usrp2/sdr_lib/cordic_stage.v fpga-src/usrp2/sdr_lib/cic_interp.v fpga-src/usrp2/sdr_lib/clip.v fpga-src/usrp2/sdr_lib/clip_reg.v fpga-src/usrp2/sdr_lib/round.v fpga-src/usrp2/sdr_lib/cordic.v fpga-src/usrp2/sdr_lib/cic_dec_shifter.v fpga-src/usrp2/sdr_lib/hb/halfband_decim.v fpga-src/usrp2/sdr_lib/clip_and_round.v fpga-src/usrp2/sdr_lib/round_tb.v fpga-src/usrp2/sdr_lib/cic_decim.v fpga-src/usrp2/sdr_lib/cic_int_shifter.v fpga-src/usrp2/sdr_lib/clip_and_round_reg.v fpga-src/usrp2/sdr_lib/cic_strober.v fpga-src/usrp2/sdr_lib/sign_extend.v fpga-src/usrp1/sdr_lib/ddc.v fpga-src/usrp1/sdr_lib/master_control.v fpga-src/usrp1/sdr_lib/clk_divider.v fpga-src/usrp1/sdr_lib/tx_chain_hb.v fpga-src/usrp1/sdr_lib/duc.v fpga-src/usrp1/sdr_lib/tx_buffer.v fpga-src/usrp1/sdr_lib/cordic_stage.v fpga-src/usrp1/sdr_lib/cic_interp.v fpga-src/usrp1/sdr_lib/rx_chain_dual.v fpga-src/usrp1/sdr_lib/cordic.v fpga-src/usrp1/sdr_lib/rx_chain.v fpga-src/usrp1/sdr_lib/cic_dec_shifter.v fpga-src/usrp1/sdr_lib/hb/halfband_decim.v fpga-src/usrp1/sdr_lib/dpram.v fpga-src/usrp1/sdr_lib/ext_fifo.v fpga-src/usrp1/sdr_lib/cic_decim.v fpga-src/usrp1/sdr_lib/rx_buffer.v fpga-src/usrp1/sdr_lib/strobe_gen.v fpga-src/usrp1/sdr_lib/serial_io.v fpga-src/usrp1/sdr_lib/cic_int_shifter.v fpga-src/usrp1/sdr_lib/gen_sync.v fpga-src/usrp1/sdr_lib/tx_chain.v fpga-src/usrp1/sdr_lib/sign_extend.v fpga-src/usrp1/sdr_lib/io_pins.v fpga-src/usrp1/sdr_lib/phase_acc.v fpga-src/usrp1/tb/interp_tb.v fpga-src/usrp1/tb/decim_tb.v fpga-src/usrp1/tb/justinterp_tb.v fpga-src/usrp1/tb/usrp_tasks.v fpga-src/usrp1/tb/cordic_tb.v fpga-src/usrp1/tb/fullchip_tb.v fpga-src/usrp1/models/pll.v fpga-src/usrp1/toplevel/usrp_std/usrp_std.v fpga-src/usrp1/toplevel/usrp_std/config.vh fpga-src/usrp1/toplevel/include/common_config_bottom.vh fpga-src/usrp1/toplevel/include/common_config_2rx_0tx.vh fpga-src/usrp1/toplevel/include/common_config_2rxhb_0tx.vh fpga-src/usrp1/toplevel/include/common_config_4rx_0tx.vh fpga-src/usrp1/toplevel/include/common_config_1rxhb_1tx.vh fpga-src/usrp1/toplevel/include/common_config_2rxhb_2tx.vh fpga-src/usrp1/toplevel/mrfm/shifter.v fpga-src/usrp1/toplevel/mrfm/mrfm.v fpga-src/usrp1/toplevel/sizetest/sizetest.v fpga-src/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v fpga-src/usrp1/toplevel/usrp_inband_usb/config.vh fpga-src/usrp1/toplevel/usrp_multi/config.vh fpga-src/usrp1/toplevel/usrp_multi/usrp_multi.v Copyright: (C) 2003-2008 Matt Ettus License: GPL-3+ Comment: Not used for uhd-host package Files: fpga-src/usrp2/sdr_lib/integrate.v fpga-src/usrp2/sdr_lib/hb_interp.v fpga-src/usrp2/sdr_lib/Makefile.srcs fpga-src/usrp2/sdr_lib/small_hb_int_tb.v fpga-src/usrp2/sdr_lib/dspengine_8to16.v fpga-src/usrp2/sdr_lib/pipectrl.v fpga-src/usrp2/sdr_lib/add2.v fpga-src/usrp2/sdr_lib/add2_and_round.v fpga-src/usrp2/sdr_lib/hb_dec.v fpga-src/usrp2/sdr_lib/med_hb_int.v fpga-src/usrp2/sdr_lib/small_hb_dec_tb.v fpga-src/usrp2/sdr_lib/halfband_tb.v fpga-src/usrp2/sdr_lib/tx_control.v fpga-src/usrp2/sdr_lib/small_hb_dec.v fpga-src/usrp2/sdr_lib/dsp_rx_glue.v fpga-src/usrp2/sdr_lib/hb_dec_tb.v fpga-src/usrp2/sdr_lib/rx_dcoffset_tb.v fpga-src/usrp2/sdr_lib/rssi.v fpga-src/usrp2/sdr_lib/hb/ram16_2sum.v fpga-src/usrp2/sdr_lib/hb/ram16_2port.v fpga-src/usrp2/sdr_lib/hb/ram32_2sum.v fpga-src/usrp2/sdr_lib/hb/halfband_interp.v fpga-src/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v fpga-src/usrp2/sdr_lib/hb/mac.v fpga-src/usrp2/sdr_lib/hb/acc.v fpga-src/usrp2/sdr_lib/hb/mult.v fpga-src/usrp2/sdr_lib/hb/coeff_ram.v fpga-src/usrp2/sdr_lib/hb/coeff_rom.v fpga-src/usrp2/sdr_lib/duc_chain.v fpga-src/usrp2/sdr_lib/acc.v fpga-src/usrp2/sdr_lib/dspengine_16to8.v fpga-src/usrp2/sdr_lib/hb_interp_tb.v fpga-src/usrp2/sdr_lib/hb_tb.v fpga-src/usrp2/sdr_lib/rx_dcoffset.v fpga-src/usrp2/sdr_lib/dummy_rx.v fpga-src/usrp2/sdr_lib/halfband_ideal.v fpga-src/usrp2/sdr_lib/dsp_tx_glue.v fpga-src/usrp2/sdr_lib/pipestage.v fpga-src/usrp2/sdr_lib/ddc_chain.v fpga-src/usrp2/sdr_lib/add2_reg.v fpga-src/usrp2/sdr_lib/small_hb_int.v fpga-src/usrp2/sdr_lib/add2_and_round_reg.v fpga-src/usrp2/sdr_lib/rx_control.v fpga-src/usrp2/serdes/Makefile.srcs fpga-src/usrp2/serdes/serdes.v fpga-src/usrp2/serdes/serdes_rx.v fpga-src/usrp2/serdes/serdes_tx.v fpga-src/usrp2/serdes/serdes_fc_tx.v fpga-src/usrp2/serdes/serdes_fc_rx.v fpga-src/usrp2/serdes/serdes_tb.v fpga-src/usrp2/fifo/dsp_framer36.v fpga-src/usrp2/fifo/Makefile.srcs fpga-src/usrp2/fifo/fifo36_to_fifo19.v fpga-src/usrp2/fifo/fifo19_mux.v fpga-src/usrp2/fifo/packet_tb.v fpga-src/usrp2/fifo/buffer_int2.v fpga-src/usrp2/fifo/fifo19_to_ll8.v fpga-src/usrp2/fifo/packet_verifier.v fpga-src/usrp2/fifo/buffer_int.v fpga-src/usrp2/fifo/fifo_2clock.v fpga-src/usrp2/fifo/fifo19_pad.v fpga-src/usrp2/fifo/packet_generator32.v fpga-src/usrp2/fifo/fifo36_to_ll8.v fpga-src/usrp2/fifo/packet_verifier32.v fpga-src/usrp2/fifo/fifo_19to36_tb.v fpga-src/usrp2/fifo/packet_dispatcher36_x3.v fpga-src/usrp2/fifo/buffer_pool_tb.v fpga-src/usrp2/fifo/fifo_2clock_cascade.v fpga-src/usrp2/fifo/fifo_tb.v fpga-src/usrp2/fifo/fifo72_to_fifo36.v fpga-src/usrp2/fifo/fifo36_to_fifo72.v fpga-src/usrp2/fifo/packet_router.v fpga-src/usrp2/fifo/fifo19_to_fifo36.v fpga-src/usrp2/fifo/crossbar36.v fpga-src/usrp2/fifo/splitter36.v fpga-src/usrp2/fifo/fifo_long.v fpga-src/usrp2/fifo/buffer_int_tb.v fpga-src/usrp2/fifo/packet32_tb.v fpga-src/usrp2/fifo/fifo_short.v fpga-src/usrp2/fifo/ll8_to_fifo19.v fpga-src/usrp2/fifo/ll8_shortfifo.v fpga-src/usrp2/fifo/packet_generator.v fpga-src/usrp2/fifo/fifo_pacer.v fpga-src/usrp2/fifo/fifo36_mux.v fpga-src/usrp2/fifo/ll8_to_fifo36.v fpga-src/usrp2/fifo/fifo36_demux.v fpga-src/usrp2/fifo/buffer_pool.v fpga-src/usrp2/fifo/fifo_cascade.v fpga-src/usrp2/fifo/add_routing_header.v fpga-src/usrp2/fifo/valve36.v fpga-src/usrp2/control_lib/Makefile.srcs fpga-src/usrp2/control_lib/bin2gray.v fpga-src/usrp2/control_lib/mux_32_4.v fpga-src/usrp2/control_lib/mux8.v fpga-src/usrp2/control_lib/srl.v fpga-src/usrp2/control_lib/settings_bus_16LE.v fpga-src/usrp2/control_lib/reset_sync.v fpga-src/usrp2/control_lib/ram_harv_cache.v fpga-src/usrp2/control_lib/quad_uart.v fpga-src/usrp2/control_lib/gray2bin.v fpga-src/usrp2/control_lib/user_settings.v fpga-src/usrp2/control_lib/wb_output_pins32.v fpga-src/usrp2/control_lib/double_buffer.v fpga-src/usrp2/control_lib/shortfifo.v fpga-src/usrp2/control_lib/oneshot_2clk.v fpga-src/usrp2/control_lib/ram_harvard.v fpga-src/usrp2/control_lib/settings_bus.v fpga-src/usrp2/control_lib/sd_spi_wb.v fpga-src/usrp2/control_lib/wb_bridge_16_32.v fpga-src/usrp2/control_lib/clock_control.v fpga-src/usrp2/control_lib/longfifo.v fpga-src/usrp2/control_lib/dbsm.v fpga-src/usrp2/control_lib/simple_uart.v fpga-src/usrp2/control_lib/bootram.v fpga-src/usrp2/control_lib/sd_spi_tb.v fpga-src/usrp2/control_lib/system_control.v fpga-src/usrp2/control_lib/wb_semaphore.v fpga-src/usrp2/control_lib/dpram32.v fpga-src/usrp2/control_lib/dcache.v fpga-src/usrp2/control_lib/clock_bootstrap_rom.v fpga-src/usrp2/control_lib/v5icap_wb.v fpga-src/usrp2/control_lib/s3a_icap_wb.v fpga-src/usrp2/control_lib/priority_enc.v fpga-src/usrp2/control_lib/simple_uart_tx.v fpga-src/usrp2/control_lib/wb_regfile_2clock.v fpga-src/usrp2/control_lib/gray_send.v fpga-src/usrp2/control_lib/decoder_3_8.v fpga-src/usrp2/control_lib/wb_ram_dist.v fpga-src/usrp2/control_lib/wb_bus_writer.v fpga-src/usrp2/control_lib/traffic_cop.v fpga-src/usrp2/control_lib/icache.v fpga-src/usrp2/control_lib/setting_reg.v fpga-src/usrp2/control_lib/wb_sim.v fpga-src/usrp2/control_lib/atr_controller16.v fpga-src/usrp2/control_lib/ram_2port_mixed_width.v fpga-src/usrp2/control_lib/atr_controller.v fpga-src/usrp2/control_lib/ram_2port.v fpga-src/usrp2/control_lib/ss_rcvr.v fpga-src/usrp2/control_lib/wb_readback_mux_16LE.v fpga-src/usrp2/control_lib/ram_harvard2.v fpga-src/usrp2/control_lib/settings_bus_crossclock.v fpga-src/usrp2/control_lib/fifo_to_wb.v fpga-src/usrp2/control_lib/mux4.v fpga-src/usrp2/control_lib/fifo_to_wb_tb.v fpga-src/usrp2/control_lib/double_buffer_tb.v fpga-src/usrp2/control_lib/medfifo.v fpga-src/usrp2/control_lib/simple_uart_rx.v fpga-src/usrp2/control_lib/ram_loader.v fpga-src/usrp2/control_lib/system_control_tb.v fpga-src/usrp2/control_lib/ram_wb_harvard.v fpga-src/usrp2/control_lib/spi.v fpga-src/usrp2/control_lib/sd_spi.v fpga-src/usrp2/control_lib/clock_control_tb.v fpga-src/usrp2/control_lib/wb_ram_block.v fpga-src/usrp2/control_lib/gpio_atr.v fpga-src/usrp2/control_lib/wb_readback_mux.v fpga-src/usrp2/udp/Makefile.srcs fpga-src/usrp2/udp/add_onescomp.v fpga-src/usrp2/udp/prot_eng_tx_tb.v fpga-src/usrp2/udp/udp_wrapper.v fpga-src/usrp2/udp/prot_eng_tx.v fpga-src/usrp2/udp/fifo19_rxrealign.v fpga-src/usrp2/udp/prot_eng_rx.v fpga-src/usrp2/opencores/Makefile.srcs fpga-src/usrp2/gpif/Makefile.srcs fpga-src/usrp2/gpif/packet_reframer.v fpga-src/usrp2/gpif/packet_splitter.v fpga-src/usrp2/gpif/gpif_wr_tb.v fpga-src/usrp2/gpif/slave_fifo.v fpga-src/usrp2/gpif/gpif_tb.v fpga-src/usrp2/gpif/gpif_wr.v fpga-src/usrp2/gpif/gpif.v fpga-src/usrp2/gpif/gpif_rd.v fpga-src/usrp2/gpif/packet_splitter_tb.v fpga-src/usrp2/testbench/single_u2_sim.v fpga-src/usrp2/coregen/Makefile.srcs fpga-src/usrp2/vrt/Makefile.srcs fpga-src/usrp2/vrt/vita_rx_control.v fpga-src/usrp2/vrt/gen_context_pkt.v fpga-src/usrp2/vrt/vita_rx_tb.v fpga-src/usrp2/vrt/vita_tx_chain.v fpga-src/usrp2/vrt/trigger_context_pkt.v fpga-src/usrp2/vrt/vita_pkt_gen.v fpga-src/usrp2/vrt/vita_rx_chain.v fpga-src/usrp2/vrt/vita_tx_deframer.v fpga-src/usrp2/vrt/vita_tx_engine_glue.v fpga-src/usrp2/vrt/vita_rx_framer.v fpga-src/usrp2/vrt/vita_tx_control.v fpga-src/usrp2/vrt/vita_rx_engine_glue.v fpga-src/usrp2/vrt/vita_tx_tb.v fpga-src/usrp2/timing/Makefile.srcs fpga-src/usrp2/timing/time_compare.v fpga-src/usrp2/timing/timer.v fpga-src/usrp2/timing/time_transfer_tb.v fpga-src/usrp2/timing/time_sender.v fpga-src/usrp2/timing/time_64bit.v fpga-src/usrp2/timing/time_sync.v fpga-src/usrp2/timing/time_receiver.v fpga-src/usrp2/timing/simple_timer.v fpga-src/usrp2/gpmc/Makefile.srcs fpga-src/usrp2/gpmc/cross_clock_reader.v fpga-src/usrp2/gpmc/gpmc_wb.v fpga-src/usrp2/gpmc/fifo_to_gpmc.v fpga-src/usrp2/gpmc/gpmc_to_fifo.v fpga-src/usrp2/gpmc/gpmc.v fpga-src/usrp2/simple_gemac/eth_tasks_f36.v fpga-src/usrp2/simple_gemac/Makefile.srcs fpga-src/usrp2/simple_gemac/crc.v fpga-src/usrp2/simple_gemac/flow_ctrl_rx.v fpga-src/usrp2/simple_gemac/simple_gemac_wrapper_tb.v fpga-src/usrp2/simple_gemac/simple_gemac.v fpga-src/usrp2/simple_gemac/simple_gemac_tx.v fpga-src/usrp2/simple_gemac/simple_gemac_tb.v fpga-src/usrp2/simple_gemac/ll8_to_txmac.v fpga-src/usrp2/simple_gemac/simple_gemac_wb.v fpga-src/usrp2/simple_gemac/simple_gemac_wrapper.v fpga-src/usrp2/simple_gemac/rxmac_to_ll8.v fpga-src/usrp2/simple_gemac/flow_ctrl_tx.v fpga-src/usrp2/simple_gemac/eth_tasks.v fpga-src/usrp2/simple_gemac/ethtx_realign.v fpga-src/usrp2/simple_gemac/address_filter.v fpga-src/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v fpga-src/usrp2/simple_gemac/simple_gemac_rx.v fpga-src/usrp2/simple_gemac/delay_line.v fpga-src/usrp2/simple_gemac/address_filter_promisc.v fpga-src/usrp2/simple_gemac/ethrx_realign.v fpga-src/usrp2/simple_gemac/eth_tasks_f19.v fpga-src/usrp2/models/M24LC02B.v fpga-src/usrp2/models/CY7C1356C/cy1356.v fpga-src/usrp2/models/CY7C1356C/testbench.v fpga-src/usrp2/models/cpld_model.v fpga-src/usrp2/models/adc_model.v fpga-src/usrp2/models/serdes_model.v fpga-src/usrp2/models/MULT18X18S.v fpga-src/usrp2/models/gpmc_model_async.v fpga-src/usrp2/models/xlnx_glbl.v fpga-src/usrp2/models/gpmc_model_sync.v fpga-src/usrp2/models/miim_model.v fpga-src/usrp2/models/uart_rx.v fpga-src/usrp2/models/M24LC024B.v fpga-src/usrp2/models/math_real.v fpga-src/usrp2/custom/power_trig_tb.v fpga-src/usrp2/custom/custom_dsp_tx.v fpga-src/usrp2/custom/custom_engine_tx.v fpga-src/usrp2/custom/custom_engine_rx.v fpga-src/usrp2/custom/power_trig.v fpga-src/usrp2/custom/custom_dsp_rx.v fpga-src/usrp2/extramfifo/Makefile.srcs fpga-src/usrp2/extramfifo/nobl_fifo.v fpga-src/usrp2/extramfifo/refill_randomizer.v fpga-src/usrp2/extramfifo/nobl_if.v fpga-src/usrp2/extramfifo/ext_fifo.v fpga-src/usrp2/extramfifo/test_sram_if.v fpga-src/usrp2/extramfifo/ext_fifo_tb.v fpga-src/usrp2/top/python/check_timing.py fpga-src/usrp2/top/python/check_inout.py fpga-src/usrp2/top/tcl/ise_helper.tcl fpga-src/usrp2/top/USRP2/u2_rev3.v fpga-src/usrp2/top/USRP2/u2_core.v fpga-src/usrp2/top/USRP2/Makefile fpga-src/usrp2/top/Makefile.common fpga-src/usrp2/top/E1x0/u1e.v fpga-src/usrp2/top/E1x0/Makefile.E100 fpga-src/usrp2/top/E1x0/tb_u1e.v fpga-src/usrp2/top/E1x0/Makefile.E110 fpga-src/usrp2/top/E1x0/u1e_core.v fpga-src/usrp2/top/E1x0/Makefile fpga-src/usrp2/top/B100/u1plus.v fpga-src/usrp2/top/B100/u1plus_core.v fpga-src/usrp2/top/B100/B100.v fpga-src/usrp2/top/B100/Makefile.B100 fpga-src/usrp2/top/B100/Makefile fpga-src/usrp2/top/N2x0/Makefile.N210R3 fpga-src/usrp2/top/N2x0/u2plus.v fpga-src/usrp2/top/N2x0/u2plus_core.v fpga-src/usrp2/top/N2x0/capture_ddrlvds.v fpga-src/usrp2/top/N2x0/Makefile.N200R4 fpga-src/usrp2/top/N2x0/Makefile.N200R3 fpga-src/usrp2/top/N2x0/Makefile.N210R4 fpga-src/usrp2/top/N2x0/Makefile Copyright: 2008-2018 Ettus Research, A National Instruments Company License: GPL-3+ Comment: Not used for uhd-host package Files: fpga-src/usrp1/megacells/* fpga-src/usrp1/toplevel/*.qsf fpga-src/usrp1/toplevel/*.qpf Copyright: (C) 1991-2004 Altera Corporation License: Altera-boilerplate Comment: Boilerplate terms prepended to files which include design parameters for the project licensed GPL-3+. . Not used for uhd-host package Files: fpga-src/usrp2/coregen/fifo* fpga-src/usrp2/models/FIFO_GENERATOR_V4_3.v fpga-src/usrp2/models/FIFO_GENERATOR_V4_3.v fpga-src/usrp2/models/BUFG.v fpga-src/usrp2/models/IOBUF.v fpga-src/usrp2/models/RAMB16_S36_S36.v fpga-src/usrp2/models/RAMB16_S36_S36.v fpga-src/usrp2/models/SRLC16E.v fpga-src/usrp2/models/SRL16E.v fpga-src/usrp2/models/FIFO_GENERATOR_V6_1.v fpga-src/usrp2/extramfifo/icon.v fpga-src/usrp2/extramfifo/ila.v Copyright: (c) 1995-2010 Xilinx, Inc. License: Xilinx-boilerplate Comment: Boilerplate terms prepended to files which include design parameters for the project licensed GPL-3+. . Not used for uhd-host package. Files: fpga-src/usrp2/opencores/8b10b Copyright: (c)2002 Chuck Benz, Hollis, NH License: Benz Comment: Not used for uhd-host package Files: fpga-src/usrp2/opencores/aemb Copyright: (C) 2004-2007 Shawn Tan Ser Ngiap License: AEMB-LGPL-3+ Files: fpga-src/usrp2/opencores/i2c/* fpga-src/usrp2/opencores/simple_gpio/* fpga-src/usrp2/opencores/simple_pic/* Copyright: (C) 2000,2001,2002,2004 Richard Herveille License: Herveille Comment: Not used for uhd-host package Files: fpga-src/usrp2/opencores/spi Copyright: (C) 2002 Simon Srot (simons@opencores.org) License: Srot-LGPL-2.1+ Comment: Not used for uhd-host package Files: fpga-src/usrp2/opencores/spi_boot/* Copyright: (c) 2005, Arnim Laeuger (arniml@opencores.org) License: GPL-2 Comment: COPYING file is GPL-2. . On Debian systems, the complete text of the GNU General Public License can be found in `/usr/share/common-licenses/GPL-2'. . Not used for uhd-host package Files: fpga-src/usrp2/opencores/wb_zbt Copyright: (C) 2008 Sebastien Bourdeauducq - http://lekernel.net License: Milkymist-LGPL-2+ Comment: Not used for uhd-host package Files: fpga-src/usrp2/opencores/zpu/* Copyright: 2004-2008 oharboe - �yvind Harboe - oyvind.harboe@zylin.com License: zpu-FreeBSD Comment: Not used for uhd-host package Files: mpm/lib/mykonos/adi/* Copyright: Copyright (c) 2015-2017 Analog Devices Inc. License: AD9371-API Comment: Not used for uhd-host package License: GPL-2+ This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 2 of the License, or (at your option) any later version. . This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 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License: Altera-boilerplate Any megafunction design, and related netlist (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, netlist, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. 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This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. . This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. . You should have received a copy of the GNU Lesser General Public License along with this source; if not, download it from http://www.opencores.org/lgpl.shtml . On Debian systems, the complete text of the GNU Lesser General Public License can be found in `/usr/share/common-licenses/LGPL-2.1'. License: GPL-2 Redistribution and use in source and synthezised forms, with or without modification, are permitted provided that the following conditions are met: . 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