The top is defined in HDL source file common_regs.v, x4xx.v.
Target Regmap = AXI_HPM0_REGMAP
This port is defined in HDL source file common_regs.v.
Source Window = PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW
This port is defined in HDL source file common_regs.v.
Source Window = PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW
This port is defined in HDL source file common_regs.v.
Target Regmap = MB_CPLD_PS_REGMAP
This port is defined in HDL source file common_regs.v.
This is the map for the register space that the Processing System's M_AXI_HPM0_FPD port (AXI4 master interface) has access to. This port has a 40-bit address bus.
|
|
|
This window is defined in HDL source file common_regs.v.
Space reserved for RPU access
|
|
|
This window is defined in HDL source file common_regs.v.
Register space for the JTAG engine for MB CPLD programming.
|
|
|
This window is defined in HDL source file common_regs.v.
Register space reserved for future use.
Target regmap = PL_CPLD_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file common_regs.v.
MPM endpoint fro MB/DB communication.
Target regmap = CORE_REGS_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file common_regs.v.
Register space reserved for mboard-regs (Core).
Target regmap = ETH_DMA_CTRL_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file common_regs.v.
AXI DMA engine for internal Ethernet interface.
|
|
|
This window is defined in HDL source file common_regs.v.
Misc. registers for internal Ethernet.
|
|
|
This window is defined in HDL source file common_regs.v.
Register space occupied by the Xilinx RFDC IP block.
Target regmap = RFDC_REGS_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file common_regs.v.
Register space for RFDC control/status registers.
Target regmap = QSFP_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file uhd_regs.v.
Target regmap = QSFP_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file uhd_regs.v.
Target regmap = QSFP_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file uhd_regs.v.
Target regmap = QSFP_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file uhd_regs.v.
Target regmap = QSFP_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file uhd_regs.v.
Target regmap = QSFP_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file uhd_regs.v.
Target regmap = QSFP_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file uhd_regs.v.
Target regmap = QSFP_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file uhd_regs.v.
This register map is available using the PS CPLD SPI interface.
Target regmap = PS_CPLD_BASE_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file mb_cpld.v.
Target regmap = RECONFIG_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file mb_cpld.v.
Target regmap = PS_POWER_REGMAP
(show extended info)
|
|
|
This window is defined in HDL source file mb_cpld.v.
Target regmap = GLOBAL_REGS_REGMAP
(show extended info)
|
|
|
|
This window is defined in HDL source file x4xx_core_common.v.
Target regmap = VERSIONING_REGS_REGMAP
(show extended info)
|
|
|
|
This window is defined in HDL source file x4xx_core_common.v.
|
|
|
|
This window is defined in HDL source file x4xx_core_common.v.
Target regmap = DIO_REGMAP
(show extended info)
|
|
|
|
This window is defined in HDL source file x4xx_core_common.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file cpld_interface_regs.v.
| Bits | Name |
| 31..0 |
fixed value 0xCB1D1FAC |
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file cpld_interface_regs.v.
|
|
|
|
|
Initial Value = 0x00000002
This register is defined in HDL source file cpld_interface_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..0 |
Divider value |
|
|
|
|
|
Initial Value = 0x00000005
This register is defined in HDL source file cpld_interface_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..0 |
Divider value |
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file cpld_interface_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..1 |
Reserved |
| 0 |
If 1 enables the forwarding of iPass cable present signal to MB CPLD using ctrlport requests. On change from 0 to 1 the current status is transferred to the MB CPLD via SPI ctrlport request initially. |
|
|
|
|
|
|||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_dio.v.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
|
|
|
|
|
|||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_dio.v.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
|
|
|
|
|
|||||||||
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_dio.v.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
|
|
|
|
|
|||||||||
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_dio.v.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
|
|
|
|
This window is defined in HDL source file common_regs.v.
|
|
|
|
This window is defined in HDL source file common_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..16 | |
| 15..0 |
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..27 | |
| 26..23 | |
| 22..17 |
This is the year number after 2000 (e.g. 2019 = d19). |
| 16..12 | |
| 11..6 | |
| 5..0 |
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31 |
Set to 1 if PCI-Express core is present in FPGA design. |
| 30..24 |
Reserved |
| 23..16 |
Reserved |
| 15..0 |
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..16 | |
| 15..8 | |
| 7..0 |
|
|
|
|
|
Initial Value = 0x00000000
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..24 |
Number of base reference clock cycles from appearance of the PPS
rising edge to the occurrence of the aligned edge of base reference
clock and PLL reference clock at the sample PLL output. This number
is the sum of the actual value based on PLL_SYNC_DELAY (also
accumulate the fixed amount of clock cycles) and if any the number of
cycles the SPLL requires from issuing of the SYNC signal to the
aligned edge (with LMK04832 = 0). |
| 23..16 |
Due to the HDL implementation the rising edge of the SYNC signal for
the LMK04832 is generated 2 clock cycles after the PPS rising edge.
This delay can be further increased by setting this delay value
(e.g. PLL_SYNC_DELAY=3 will result in a total delay of 5 clock cycles). |
| 15..10 |
Reserved |
| 9r |
Indicates the success of the PLL reset started by PLL_SYNC_TRIGGER. Reset on deassertion of PLL_SYNC_TRIGGER. |
| 8w |
Assertion triggers the SYNC signal generation for LMK04832 after the next appearance of the PPS rising edge. There is no self reset on this trigger. Keep this trigger asserted until PLL_SYNC_DONE is asserted. |
| 7..6 |
Reserved |
| 5..4 |
TRIGGER_IO_SELECT (initialvalue=TRIG_IO_INPUT) IMPORTANT! SW must ensure any TRIG_IO consumers (downstream devices) ignore and/or re-sync after enabling this port, since the output-enable is basically asynchronous to the actual TRIG_IO driver. The values for this bitfield are in the TRIG_IO_ENUM table. (show here) |
| 3r |
RESERVED. This bit is not implemented on X4xx and reads as 0. |
| 2 |
RESERVED. This bit is not implemented on X4xx and reads as 0. |
| 1..0 |
PPS_SELECT (initialvalue=PPS_INT_25MHZ) Select the source of the PPS signal. For the internal generation the value depending on the base reference clock has to be chosen. The external reference is taken from the PPS_IN pin and is independent of the base reference clock. The values for this bitfield are in the PPS_ENUM table. (show here) |
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31 |
Enables the PPS signal in radio clock domain. Please make sure that the values of PPS_BRC_DELAY, PPS_PRC_DELAY and PRC_RC_DIVIDER are set before enabling this bit. It is recommended to disable the PPS for changes on the other values. Use a wait time of at least 1 second before changing this value to ensure the values are stable for the next PPS edge. |
| 30 |
Reserved |
| 29..28 |
Clock multiplier used to generate radio clock from PLL reference clock. The value written to the register has to be reduced by 2 due to HDL implementation. |
| 27..26 |
Reserved |
| 25..0 |
The number of PLL reference clock cycles from one aligned edge to the
desired aligned edge to issue the PPS in radio clock domain. This
delay is configurable to any aligned edge within a maximum delay of 1
second (period of PPS). |
|
|
|
|
|
Initial Value = 0x0BEBC200
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..0 |
CHDR_CLK (initialvalue=CHDR_CLK_VALUE) The values for this bitfield are in the CHDR_CLK_ENUM table. (show here) |
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..2 |
Reserved |
| 1 |
When enabled, routes data_clk to FPGA_REF_CLK output port. When disabled, the FPGA_REF_CLK output is driven to 0. |
| 0 |
When enabled, routes data_clk to GTY_RCV_CLK output port. When disabled, the GTY_RCV_CLK output is driven to 0. |
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
| Bits | Name |
| 31..26 |
Reserved |
| 25..0 |
Report the time between rising edges on the FPGA_REF_CLK input port in 40 MHz Clock ticks. If the count extends to 1.2 seconds without an edge, the value reported is set to zero. |
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_global_regs.v.
This register map is present for each JTAG module.
Basic operation would be:
For resetting the BITQ FSM, simply assert reset.
This operation seems a little strange, but it is what the axi_bitq driver expects. This behavior has been implemented in previous products.
|
|
|
|
|
|
|||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file ctrlport_to_jtag.v.
Data to be transmitted (TDI)
|
|
|
|
|
|
|||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file ctrlport_to_jtag.v.
Data to be transmitted (TMS)
|
|
|
|
|
|
|||||||||||
|
|
Initial Value = 0x00000001
This register is defined in HDL source file ctrlport_to_jtag.v.
JTAG module status and control
| Bits | Name |
| 31r |
Bitq FSM is ready for input (no data transmission in progress). |
| 31w | |
| 30..24 |
Reserved |
| 23..16 |
Reserved |
| 15..13 |
Reserved |
| 12..8 |
(Number of bits - 1) to be transferred |
| 7..0 |
Clock divider. Resulting JTAG frequency will be f_ctrlport / (2*(prescalar + 1)). See window description for details on the initial/minimum value. |
|
|
|
|
|
|
|||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file ctrlport_to_jtag.v.
Received data (TDO)
This register map is available using the PL CPLD SPI interface. All protocol masters controller by this register map are running with a clock frequency of 50 MHz.
Target regmap = PL_CPLD_BASE_REGMAP
(show extended info)
|
|
|
|
|
This window is defined in HDL source file mb_cpld.v.
Target regmap = JTAG_REGMAP
(show extended info)
|
|
|
|
|
This window is defined in HDL source file mb_cpld.v.
JTAG Master connected to first daugherboard's CPLD JTAG interface.
Use minimum value of 1 for JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.
Target regmap = JTAG_REGMAP
(show extended info)
|
|
|
|
|
This window is defined in HDL source file mb_cpld.v.
JTAG Master connected to second daugherboard's CPLD JTAG interface.
Use minimum value of 1 for JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.
nixge (maps to 10g mac if present)
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
| Bits | Name |
| 31..24 |
Constant indicating version for this space. Not used by the NIXGE driver (12/4/2020) |
| 23..18 |
Reserved |
| 17 |
Generically this mirrors the activity LED. Specific meaning varies based on the MGT_PROTOCOL. |
| 16 |
Generically means that a connection with a peer has been established. Specific meaning varies based on the MGT_PROTOCOL. |
| 15..8 |
Constant indicating what flavor of communication this port is using
|
| 7..0 |
Constant indicating which port this register is hooked to
|
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Definition of this register depends on Protocol
10GBE
READ - Status
WRITE - Ctl
100 GBE
READ - Status
WRITE - Ctl
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Definition of this register depends on Protocol
10GBE
*READ - Status *
100 GBE
READ - Status
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..2 |
Reserved |
| 1 |
When identify_enable is set, this value controls the activity LED. |
| 0 |
When set identify_value is used to control the activity LED. When clear the activity LED set on any TX or RX traffic to the mgt |
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
The x4xx family of products does not use MDIO.
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Only valid if the protocol is Aurora.
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Only valid if the protocol is Aurora.
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Only valid if the protocol is Aurora.
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Only valid if the protocol is Aurora.
Target regmap = XGE_MAC_REGMAP
(show extended info)
|
|
|
|
|
||||||||||
|
|
|||||||||||||
|
|
|||||||||||||
|
|
|||||||||||||
|
|
|||||||||||||
|
|
|||||||||||||
|
|
|||||||||||||
|
|
This window is defined in HDL source file uhd_regs.v.
|
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
| Bits | Name |
| 15..12 |
Active LEDs of QSFP port 1 |
| 11..8 |
Link LEDs of QSFP port 1 |
| 7..4 |
Active LEDs of QSFP port 0 |
| 3..0 |
Link LEDs of QSFP port 0 |
|
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
| Bits | Name |
| 1 |
Set to 1 if cable present in iPass 1 connector. |
| 0 |
Set to 1 if cable present in iPass 0 connector. |
|
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
| Bits | Name |
| 31..0 |
Fixed value PL_CPLD_SIGNATURE of CONSTANTS_REGMAP |
|
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
| Bits | Name |
| 31..24 |
Contains revision year code. |
| 23..16 |
Contains revision month code. |
| 15..8 |
Contains revision day code. |
| 7..0 |
Contains revision hour code. |
|
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
| Bits | Name |
| 31..24 |
Contains revision year code. |
| 23..16 |
Contains revision month code. |
| 15..8 |
Contains revision day code. |
| 7..0 |
Contains revision hour code. |
|
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
|
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file pl_cpld_regs.v.
| Bits | Name |
| 31..28 |
0x0 in case the git status was clean |
| 27..0 |
7 hex digit hash code of the commit |
Target regmap = CPLD_INTERFACE_REGMAP
(show extended info)
|
|
|
|
This window is defined in HDL source file cpld_interface.v.
Target regmap = MB_CPLD_PL_REGMAP
(show extended info)
|
|
|
|
This window is defined in HDL source file cpld_interface.v.
|
|
|
|
This window is defined in HDL source file cpld_interface.v.
|
|
|
|
This window is defined in HDL source file cpld_interface.v.
Target port = X4XX_FPGA|ARM_S_AXI_HPC0
(show extended info)
|
This window is defined in HDL source file common_regs.v.
| Offset | Size | Description |
|---|---|---|
| 0x000800000000 | 0x000800000000 | DDR_HIGH |
| 0x00000000 | 0x80000000 | DDR_LOW |
| 0xFF000000 | 0x01000000 | LPS_OCM |
| 0xC0000000 | 0x20000000 | QSPI |
Target port = X4XX_FPGA|ARM_S_AXI_HPC1
(show extended info)
|
This window is defined in HDL source file common_regs.v.
| Offset | Size | Description |
|---|---|---|
| 0x000800000000 | 0x000800000000 | DDR_HIGH |
| 0x00000000 | 0x80000000 | DDR_LOW |
| 0xC0000000 | 0x20000000 | QSPI |
|
|
|
|
Initial Value = 0x00000000
This register is defined in HDL source file ps_cpld_regs.v.
| Bits | Name |
| 31..28 |
Reserved |
| 27..16 | |
| 15..12 |
Reserved |
| 11..0 |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
|
|
|
|
Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
|
|
|
|
Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
| Bits | Name |
| 31r |
1 if an upstream CMI device has been detected. |
| 30..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..1 |
Reserved |
| 0 |
Set if the device is ready to establish a PCI-Express link (affects CMI_CLP_READY bit). |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..22 |
Reserved |
| 21w |
Writing with this flag set asserts reset for DB 1 (overrides RELEASE_RESET_DB1) |
| 20w |
Writing with this flag set asserts reset for DB 0 (overrides RELEASE_RESET_DB0) |
| 19..18 |
Reserved |
| 17w |
Writing with this flag set releases DB 1 reset. (may be overwritten by ASSERT_RESET_DB1) |
| 16w |
Writing with this flag set releases DB 0 reset. (may be overwritten by ASSERT_RESET_DB0) |
| 15 |
Reserved |
| 14w |
Writing with this flag set disables the PLL reference clock (overrides ENABLE_PLL_REF_CLOCK). Assert this flag to reconfigure the clock. |
| 13w |
Writing with this flag set disables DB 1 clock forwarding (overrides ENABLE_CLOCK_DB1) |
| 12w |
Writing with this flag set disables DB 0 clock forwarding (overrides ENABLE_CLOCK_DB0) |
| 11 |
Reserved |
| 10w |
Writing with this flag set enables the PLL reference clock. Assert this flag after PLL reference clock is stable. (may be overwritten by DISABLE_PLL_REF_CLOCK) |
| 9w |
Writing with this flag set enables DB 1 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB1) |
| 8w |
Writing with this flag set enables DB 0 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB0) |
| 7..6 |
Reserved |
| 5r |
Indicates that reset is asserted for DB 1. |
| 4r |
Indicates that reset is asserted for DB 0. |
| 3 |
Reserved |
| 2r |
Indicates if the PLL reference clock for the PL interface is enabled. |
| 1r |
Indicates if a clock is forwarded to DB 1. |
| 0r |
Indicates if a clock is forwarded to DB 0. |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
| Bits | Name |
| 31..0 |
Fixed value PS_CPLD_SIGNATURE of CONSTANTS_REGMAP |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
| Bits | Name |
| 31..24 |
Contains revision year code. |
| 23..16 |
Contains revision month code. |
| 15..8 |
Contains revision day code. |
| 7..0 |
Contains revision hour code. |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
| Bits | Name |
| 31..24 |
Contains revision year code. |
| 23..16 |
Contains revision month code. |
| 15..8 |
Contains revision day code. |
| 7..0 |
Contains revision hour code. |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
|
|
|
|
Initial Value not specified
This register is defined in HDL source file ps_cpld_regs.v.
| Bits | Name |
| 31..28 |
0x0 in case the git status was clean |
| 27..0 |
7 hex digit hash code of the commit |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file ps_power_regs.v.
| Bits | Name |
| 31r |
Asserted signal indicates a power fault in power switch for iPass connector 1. Sticky bit. Asserted on occurrence. Reset using IPASS_CLEAR_POWER_FAULT1. |
| 31w |
Clear IPASS_POWER_FAULT1. |
| 30r |
Asserted signal indicates a power fault in power switch for iPass connector 0. Sticky bit. Asserted on occurrence. Reset using IPASS_CLEAR_POWER_FAULT0. |
| 30w |
Clear IPASS_POWER_FAULT0. |
| 29..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..1 |
Reserved |
| 0 |
Set to 1 to disable power for both iPass connectors. |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file ps_power_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..2 |
Reserved |
| 1 |
Enables 5V power switch for the 122.88 MHz oscillator. |
| 0 |
Enables 5V power switch for the 100 MHz oscillator. |
Register space for a single QSFP Communication port. This currently breaks into 2 possible configurations
Target regmap = DMA_REGMAP
(show extended info)
|
|
|
|
||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
This window is defined in HDL source file uhd_regs.v.
Target regmap = NIXGE_REGMAP
(show extended info)
|
|
|
|
||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
This window is defined in HDL source file uhd_regs.v.
Target regmap = UIO_REGMAP
(show extended info)
|
|
|
|
||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
This window is defined in HDL source file uhd_regs.v.
Target regmap = CMAC_REGMAP
(show extended info)
|
|
|
|
||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
||||||||||
|
|
This window is defined in HDL source file uhd_regs.v.
|
This window is defined in HDL source file x4xx_core_common.v.
Target regmap = RFDC_TIMING_REGMAP
(show extended info)
|
This window is defined in HDL source file x4xx_core_common.v.
Target regmap = DIO_REGMAP
(show extended info)
|
This window is defined in HDL source file x4xx_core_common.v.
Prepare the data...
The Max 10 FPGA build should generate a *cfm0_auto.rpd file The *.rpd file is a "raw programming data" file holding all data related to the configuration image (CFM0). There are two important items to note regarding the addresses. First the *rpd data uses byte addresses. Second, the start/end addresses defined by FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses
As a sanity check, verify the size of the raw programming data for CFM0 correspond to the address range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by reading the values from FLASH_CFM0_START_ADDR_REG and FLASH_CFM0_END_ADDR, subtract both values, add one and multiply by four.
Having passed the sanity check the *.rpd data must now be manipulated into the form required by Altera's on-chip flash IP. Two operations must be performed. First the data must be converted from bytes to 32-bit words. Second the bit order must be reversed. This is illustrated in in the following table which shows byte address and data from the *.rpd file compared to the word address and data to be written to the on-chip flash.
| .Map Addr | .Map Data | Flash Addr | Flash Data |
| 0x2B800 | 0x01 | 0xAC00 | 0x8040C020 |
| 0x2B801 | 0x02 | ||
| 0x2B802 | 0x03 | ||
| 0x2B803 | 0x04 | ||
| 0x2B804 | 0x05 | 0xAC01 | 0xA060E010 |
| 0x2B805 | 0x06 | ||
| 0x2B806 | 0x07 | ||
| 0x2B807 | 0x08 |
The resulting set of flash address data pairs should be used when writing FLASH_ADDR_REG and FLASH_WRITE_DATA_REG to update the CFM0 image. However, prior to writing the new image the old image must be erased.
Erase the current primary flash image...
Write the new primary flash image...
Verify the new primary flash image...
After the flash has been erased, programmed, and verified, a power cycle is required for the new image to become active.
| Value | Name | |
| Dec | Hex | |
| 4096 | 0x01000 | |
| 8192 | 0x02000 | |
| 39936 | 0x09C00 | |
| 44032 | 0x0AC00 | |
| 75775 | 0x127FF | |
| 79871 | 0x137FF | |
This enumerated type is defined in HDL source file reconfig_engine.v.
|
|
|
|
Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..17 |
Reserved |
| 16 |
This bit is asserted when the flash can hold an image with memory initialization. |
| 15..14 |
Reserved |
| 13 |
This bit is asserted when write operation fails. Clear this error by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In the event of a write error... |
| 12 |
This bit is de-asserted when a write operation is in progress. Poll this bit after strobing the FLASH_WRITE_STB bit of FLASH_CONTROL_REG to determine when the write operation has completed, then check the FLASH_WRITE_ERR bit to verify the operation was successful. |
| 11..10 |
Reserved |
| 9 |
This bit is asserted when an erase operation fails. Clear this error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In the event of an erase error... |
| 8 |
This bit is de-asserted when an erase operation is in progress. Poll this bit after strobing the FLASH_ERASE_STB bit of FLASH_CONTROL_REG to determine when the erase operation has completed, then check the FLASH_ERASE_ERR bit to verify the operation was successful. |
| 7..6 |
Reserved |
| 5 |
This bit is asserted when a read operation fails. Clear this error by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the event of a read error... |
| 4 |
This bit is de-asserted when a read operation is in progress. Poll this bit after strobing the FLASH_READ_STB bit of FLASH_CONTROL_REG to determine when the read operation has completed, then check the FLASH_READ_ERR bit to verify the operation was successful. |
| 3..1 |
Reserved |
| 0 |
This bit is asserted when the flash is write protected and de-asserted when write protection is disabled. |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..11 |
Reserved |
| 10w |
CLEAR_FLASH_ERASE_ERROR_STB (Strobe) Strobe this bit to clear an erase error. |
| 9w |
CLEAR_FLASH_WRITE_ERROR_STB (Strobe) Strobe this bit to clear a write error. |
| 8w |
CLEAR_FLASH_READ_ERROR_STB (Strobe) Strobe this bit to clear a read error. |
| 7..5w |
Defines the sector to be erased. Has to be set latest with the
write access which starts the erase operation by strobing
FLASH_ERASE_STB. |
| 4w |
Strobe this bit to erase the primary Max10 configuration image (CFM0). |
| 3w |
Strobe this bit to write the data contained in FLASH_WRITE_DATA_REG to the flash address identified in FLASH_ADDR_REG. |
| 2w |
Strobe this bit to read data from the flash address identified in FLASH_ADDR_REG. |
| 1w |
Strobe this bit to disable write protection to the section of the Max 10 on-chip flash storing the primary configuration image (CFM0). |
| 0w |
Strobe this bit to enable write protection to the section of the Max 10 on-chip flash storing the primary configuration image (CFM0). |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..17 |
Reserved |
| 16..0 |
This field holds the target address for the next read or write operation. Set this field prior to strobing the FLASH_WRITE_STB and FLASH_READ_STB bits of FLASH_CONTROL_REG. Valid addresses are defined by the FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration. |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..0w |
Data in this register will be written to the flash at the address identified in FLASH_ADDR_REG when a successful write operation is executed. |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..0 |
This register contains data read from the flash address identified in FLASH_ADDR_REG after a successful read operation is executed. |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..0 |
Start address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM). |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file reconfig_engine.v.
| Bits | Name |
| 31..0 |
Last address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM). |
| Value | Name | |
| Dec | Hex | |
| 0 | 0x000 | |
| 100 | 0x064 | |
| 200 | 0x0C8 | |
| 400 | 0x190 | |
This enumerated type is defined in HDL source file common_regs.v.
|
|
|
|
This window is defined in HDL source file common_regs.v.
|
|
|
|
Initial Value not specified
This register is defined in HDL source file common_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15 | |
| 14 | |
| 13 | |
| 12 | |
| 11 | |
| 10 | |
| 9 | |
| 8 | |
| 7 | |
| 6 | |
| 5 | |
| 4 | |
| 3 | |
| 2 | |
| 1 | |
| 0 |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file common_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..1 |
Reserved |
| 0 |
Write a '1' to this bit to reset the MMCM. Then write a '0' to place the MMCM out of reset. |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file common_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..10 |
Reserved |
| 9 |
Write a '1' to this bit to trigger the enable sequence for the daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done is asserted. |
| 8 |
Write a '1' to this bit to trigger a reset for the daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done is asserted. |
| 7..6 |
Reserved |
| 5 |
Write a '1' to this bit to trigger the enable sequence for the daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done is asserted. |
| 4 |
Write a '1' to this bit to trigger a reset for the daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done is asserted. |
| 3..1 |
Reserved |
| 0 |
Write a '1' to this bit to reset the RF reset controller. Write a '0' once db0_fsm_reset_done asserts. |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file common_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..12 |
Reserved |
| 11 |
This bit asserts ('1') when the DB0 DAC chain reset sequence is completed. The bitfield deasserts ('0') after deasserting the issued triggered (enable or reset). |
| 10..8 |
Reserved |
| 7 |
This bit asserts ('1') when the DB0 ADC chain reset sequence is completed. The bitfield deasserts ('0') after deasserting the issued triggered (enable or reset). |
| 6..4 |
Reserved |
| 3 |
This bit asserts ('1') when the DB0 RF reset controller FSM reset sequence is completed. The bitfield deasserts ('0') after deasserting db0_fsm_reset. |
| 2..0 |
Reserved |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file common_regs.v.
| Bits | Name |
| 31..30 |
This bitfield is wired to the user's ADC (DB1) AXI-Stream TReady handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 29..28 |
This bitfield is wired to the user's ADC (DB1) AXI-Stream TValid handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 27..26 |
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream TValid handshake signals (I portion). The LSB is channel 0 and the MSB is channel 1. |
| 25..24 |
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream TValid handshake signals (Q portion). The LSB is channel 0 and the MSB is channel 1. |
| 23..22 |
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream TReady handshake signals (I portion). The LSB is channel 0 and the MSB is channel 1. |
| 21..20 |
This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream TReady handshake signals (Q portion). The LSB is channel 0 and the MSB is channel 1. |
| 19..18 |
This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream TValid handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 17..16 |
This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream TReady handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 15..14 |
This bitfield is wired to the user's ADC (DB0) AXI-Stream TReady handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 13..12 |
This bitfield is wired to the user's ADC (DB0) AXI-Stream TValid handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 11..10 |
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream TValid handshake signals (I portion). The LSB is channel 0 and the MSB is channel 1. |
| 9..8 |
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream TValid handshake signals (Q portion). The LSB is channel 0 and the MSB is channel 1. |
| 7..6 |
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream TReady handshake signals (I portion). The LSB is channel 0 and the MSB is channel 1. |
| 5..4 |
This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream TReady handshake signals (Q portion). The LSB is channel 0 and the MSB is channel 1. |
| 3..2 |
This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream TValid handshake signals. The LSB is channel 0 and the MSB is channel 1. |
| 1..0 |
This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream TReady handshake signals. The LSB is channel 0 and the MSB is channel 1. |
|
|
|
|
Initial Value = 0x00000000
This register is defined in HDL source file common_regs.v.
| Bits | Name |
| 31..30 |
FABRIC_DSP_TX_CNT_DB1 (initialvalue=0) Fabric DSP TX channel count for daughterboard 0. |
| 29..28 |
FABRIC_DSP_RX_CNT_DB1 (initialvalue=0) Fabric DSP RX channel count for daughterboard 0. |
| 27..16 |
FABRIC_DSP_BW_DB1 (initialvalue=FABRIC_DSP_BW_NONE) Fabric DSP BW in MHz for daughterboard 1. The values for this bitfield are in the FABRIC_DSP_BW_ENUM table. (show here) |
| 15..14 |
FABRIC_DSP_TX_CNT (initialvalue=0) Fabric DSP TX channel count for daughterboard 0. |
| 13..12 |
FABRIC_DSP_RX_CNT (initialvalue=0) Fabric DSP RX channel count for daughterboard 0. |
| 11..0 |
FABRIC_DSP_BW (initialvalue=FABRIC_DSP_BW_NONE) Fabric DSP BW in MHz for daughterboard 0. The values for this bitfield are in the FABRIC_DSP_BW_ENUM table. (show here) |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file common_regs.v.
| Bits | Name |
| 31..16 | |
| 15..0 |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file common_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..6 |
Reserved |
| 5 |
Enables calibration data for channel 3. |
| 4 |
Enables calibration data for channel 2. |
| 3..2 |
Reserved |
| 1 |
Enables calibration data for channel 1. |
| 0 |
Enables calibration data for channel 0. |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file common_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..12 |
Reserved |
| 11 | |
| 10 | |
| 9 | |
| 8 | |
| 7..4 |
Reserved |
| 3 | |
| 2 | |
| 1 | |
| 0 |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file common_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..17 |
Reserved |
| 16 | |
| 15..13 |
Reserved |
| 12 | |
| 11..9 |
Reserved |
| 8 | |
| 7..5 |
Reserved |
| 4 | |
| 3..1 |
Reserved |
| 0 |
|
|
|
|
Initial Value not specified
This register is defined in HDL source file common_regs.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..21 |
Reserved |
| 20 | |
| 19..17 |
Reserved |
| 16 | |
| 15..8 |
Reserved |
| 7..0 |
Reserved |
|
|
|
Initial Value not specified
This register is defined in HDL source file rfdc_timing_control.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..2 |
Reserved |
| 1r |
When 1, indicates that the NCO reset has completed. |
| 0w |
Write a 1 to this bit to start a reset the RFDC's NCO. |
|
|
|
Initial Value not specified
This register is defined in HDL source file rfdc_timing_control.v.
| Bits | Name |
| 31..24 |
Reserved |
| 23..16 |
Reserved |
| 15..8 |
Reserved |
| 7..2 |
Reserved |
| 1w |
This reset is for the gearbox on the DAC data path that is used to move data from one clock domain to another outside the RFDC. Write a 1 to this bit to send a reset pulse to the DAC gearbox. |
| 0w |
This reset is for the gearbox on the ADC data path that is used to move data from one clock domain to another outside the RFDC. Write a 1 to this bit to send a reset pulse to the ADC gearbox. |
This register map is present for each SPI master.
For information about the register content and the way to interact with the core see the documentation of the SPI master from opencores used internally.
The core is configured to operate with 16 slave signal signals, up to 128 bits per transmission and 8 bit clock divider. Only 64 bits of data are available via this register interface.
For the different SPI modes use the following table to derive the bits in CONTROL register. Only option 0 (CPOL=0, CPHA=0) has been tested.
| CPOL | CPHA | TX_NEG | RX_NEG |
|---|---|---|---|
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 |
|
Initial Value not specified
This register is defined in HDL source file ctrlport_to_spi.v.
Lower 32 bits of the received word. (RxWord[31:0])
|
Initial Value not specified
This register is defined in HDL source file ctrlport_to_spi.v.
Higher 32 bits of the received word. (RxWord[63:32])
|
Initial Value not specified
This register is defined in HDL source file ctrlport_to_spi.v.
Lower 32 bits of the received word. (TxWord[31:0])
|
Initial Value not specified
This register is defined in HDL source file ctrlport_to_spi.v.
Higher 32 bits of the received word. (TxWord[63:32])
|
Initial Value not specified
This register is defined in HDL source file ctrlport_to_spi.v.
Control register
|
Initial Value not specified
This register is defined in HDL source file ctrlport_to_spi.v.
| Bits | Name |
| 7..0 |
Clock Divider. |
|
Initial Value not specified
This register is defined in HDL source file ctrlport_to_spi.v.
| Bits | Name |
| 15..0 |
Slave select. |
UIO
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Set this port's IP address
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Set the UDP port for CHDR_traffic
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
If BRIDGE_ENABLE is set use this MAC_ID
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
If BRIDGE_ENABLE is set use this MAC_ID
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
If BRIDGE_ENABLE is set use this IP Address
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
If BRIDGE_ENABLE is set use this UDP Port for CHDR_traffic
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Bit 0 Controls the following logic
always_comb begin : bridge_mux
my_mac = bridge_en ? bridge_mac_reg : mac_reg;
my_ip = bridge_en ? bridge_ip_reg : ip_reg;
my_udp_chdr_port = bridge_en ? bridge_udp_port : udp_port;
end
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Count the number of Packets dropped that were addressed to the CHDR section.
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
Count the number of Packets dropped that were addressed to us, but not to the CHDR section.
|
|
|
|
|
|||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
||||||||||||
|
|
Initial Value not specified
This register is defined in HDL source file uhd_regs.v.
| Bits | Name |
| 31..16 |
If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause. Pause clear must be less than pause set or terrible things will happen. The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only used with 100Gb ethernet |
| 15..0 |
If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only used with 100Gb ethernet |
| Value | Name | |
| Dec | Hex | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 2 | 0x00000002 | |
| 2 | 0x00000002 | |
| 553719817 | 0x21011809 | |
This enumerated type is defined in HDL source file cpld_interface_regs.v.
| Value | Name | |
| Dec | Hex | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 1 | 0x00000001 | |
| 1 | 0x00000001 | |
| 537986582 | 0x20110616 | |
This enumerated type is defined in HDL source file db_gpio_interface.v.
| Value | Name | |
| Dec | Hex | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 4 | 0x00000004 | |
| 7 | 0x00000007 | |
| 7 | 0x00000007 | |
| 554176790 | 0x21081116 | |
This enumerated type is defined in HDL source file x4xx.v.
| Value | Name | |
| Dec | Hex | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 1 | 0x00000001 | |
| 1 | 0x00000001 | |
| 537929239 | 0x20102617 | |
This enumerated type is defined in HDL source file rf_core_100m.v.
| Value | Name | |
| Dec | Hex | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 0 | 0x00000000 | |
| 1 | 0x00000001 | |
| 1 | 0x00000001 | |
| 537929239 | 0x20102617 | |
This enumerated type is defined in HDL source file rf_core_400m.v.
| Description | Index range | Max # of components |
|---|---|---|
| Common components | 0 to 23 | 24 |
| UHD-specific components | 24 to 43 | 20 |
| LV-specific components | 44 to 63 | 20 |
| Value | Name |
| 0 | |
| 1 | |
| 2 | |
| 3 | |
| 4 | |
| 5 |
This enumerated type is defined in HDL source file x4xx_versioning_regs.v.
|
|
|
|
|
Initial Values
| default | => | 0x00000000 |
This register is defined in HDL source file x4xx_versioning_regs.v.
It uses RegType VERSION_TYPE which is defined in HDL source file x4xx_versioning_regs.v.
| Bits | Name |
| 31..23 |
Major number (max = 511): an increase reflects a breaking change. |
| 22..12 |
Minor number (max = 2047): an increase reflects a non-breaking change that the driver should be aware of. |
| 11..0 |
Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
but that should not impact the component's behavior |
|
|
|
|
|
Initial Values
| default | => | 0x00000000 |
This register is defined in HDL source file x4xx_versioning_regs.v.
It uses RegType VERSION_TYPE which is defined in HDL source file x4xx_versioning_regs.v.
| Bits | Name |
| 31..23 |
Major number (max = 511): an increase reflects a breaking change. |
| 22..12 |
Minor number (max = 2047): an increase reflects a non-breaking change that the driver should be aware of. |
| 11..0 |
Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
but that should not impact the component's behavior |
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_versioning_regs.v.
It uses RegType TIMESTAMP_TYPE which is defined in HDL source file x4xx_versioning_regs.v.
| Bits | Name |
| 31..24 |
This is the year number after 2000 (e.g. 2019 = 0x19). |
| 23..16 | |
| 15..8 | |
| 7..0 |
|
|
|
|
|
Initial Value not specified
This register is defined in HDL source file x4xx_versioning_regs.v.
It uses RegType RESERVED_TYPE which is defined in HDL source file x4xx_versioning_regs.v.