<html>
<head>
<meta http-equiv="Content-Type" content="text/html;charset=utf-8"/>
<style type="text/css">
body {
margin: 5px;
font-family: verdana, "Trebuchet MS", arial, helvetica, sans-serif;
font-size: 80%;
line-height: 1.3;
}
pre, code {
font-family: "courier new", courier, monospace;
font-size: 12px;
}
@media print {
body {
margin: 0px;
font-family: arial, helvetica, sans-serif;
font-size: 80%;
line-height: 1;
}
} a, a:link, a:visited, a:hover, a:active {
text-decoration: none;
color: #0000E0;
}
@media print {
a, a:link, a:visited, a:hover, a:active {
color: #000000;
}
}
div.regmap {
margin: 0px;
padding: 0px 0px 0px 10px;
border-top: 5px solid #A0A0C0;
}
@media print {
div.regmap {
border-top: 3px solid #A4A4A4;
}
}
h1.regmap {
font-size: 160%;
text-align: left;
font-weight: bold;
margin: 0px;
padding: 10px 0px;
color: #404080;
}
@media print {
h1.regmap {
font-size: 140%;
color: black;
}
}
p.rbmfooter {
font-weight: bold;
font-size: 120%;
color: #A04080;
padding: 0px 0px 15px 10px;
margin: 0px;
}
@media print {
p.rbmfooter {
font-size: 100%;
color: black;
padding: 0px 0px 0px 10px;
}
}
div.group {
border-top: 3px solid #A0C0A0;
margin: 10px 0px 0px 0px;
padding: 0px 0px 0px 10px;
}
@media print {
div.group {
border-top: 2px solid #A4A4A4;
}
}
h2.group {
font-size: 140%;
text-align: left;
font-weight: bold;
margin: 0px;
padding: 10px 0px 5px 0px;
color: #407040;
}
p.groupsource {
font-size: 100%;
text-align: left;
font-weight: bold;
margin: 0px;
padding: 5px 0px 0px 10px;
color: #407040;
}
@media print {
h2.group {
font-size: 120%;
color: black;
}
}
div.info {
margin: 5px 0px;
}
div.info p {
margin: 5px 0px;
padding: 0px;
}
div.info h3 {
font-size: 120%;
text-align: left;
font-weight: bold;
margin: 0px;
padding: 10px 0px;
color: #804080;
}
@media print {
div.info h3 {
font-size: 95%;
color: black;
}
}
div.info h4 {
font-size: 110%;
text-align: left;
font-weight: bold;
margin: 0px;
padding: 10px 0px;
color: #A04040;
}
@media print {
div.info h4 {
font-size: 90%;
font-weight: bold
}
}
h5 {
font-size: 100%;
text-align: left;
font-weight: bold;
margin: 0px;
padding: 10px 0px;
color: #A04040;
}
@media print {
h5 {
font-size: 80%;
font-weight: bol
}
}
div.register, div.enum {
/* border-top: 2px solid #C0C0C0; */
margin: 10px;
}
div.register h3 {
font-size: 120%;
text-align: left;
font-weight: bold;
margin: 0px;
padding: 10px 0px 5px 0px;
color: #004040;
}
@media print {
div.register h3 {
font-size: 100%;
color: black;
padding: 5px 0px 5px 0px;
}
}
div.register h3 .addrlsb {
font-size: 70%;
font-weight: lighter;
color: LightGray;
}
a.sh_addrs {
font-weight: normal;
font-size: 70%;
padding-left: 5px;
}
@media print {
a.sh_addrs {
display: none;
}
}
div.register div.sh_addrs {
color: #000080;
margin: 0px;
padding: 0px 0px 0px 10px;
display: none;
}
div.register div.sh_addrs table {
padding: 0px;
margin: 0px 0px 5px 10px;
}
div.register div.sh_addrs table td {
/* top right bottom left */
padding: 3px 5px 0px 0px;
}
div.register div.sh_addrs table td.l {
padding-left: 5px;
font-weight: bold;
}
div.enum h3 {
font-size: 120%;
text-align: left;
font-weight: bold;
margin: 0px;
padding: 10px 0px 5px 0px;
color: #800000;
}
@media print {
div.enum h3 {
font-size: 100%;
color: black;
padding: 5px 0px 5px 0px;
}
}
a.sh_enum {
font-size: 85%;
}
@media print {
a.sh_enum {
display: none;
}
}
div.sh_enum {
display: none;
}
table {
font-size: 100%;
}
@media print {
table {
font-size: 75%;
}
table table {
font-size: 100%;
}
}
table.bitfields, table.enum {
border: 1px solid #C0C0C0;
margin-left: 20px;
}
table.enum {
margin-top: 5px;
}
table.bitfields td, table.enum td {
padding: 3px 8px;
}
table.enum td {
border-top: 1px solid #D8D8D8;
}
table.bitfields tr.byte td {
border-top: 1px solid #D8D8D8;
}
table.bitfields tr.header td, table.enum tr.header td,
table.enum tr.header2 td {
font-weight: bold;
color: #004080;
background-color: #F0F0F0;
padding-top: 1px;
padding-bottom: 1px;
}
@media print {
table.bitfields tr.header td, table.enum tr.header td,
table.enum tr.header2 td {
color: black;
}
}
table.bitfields tr.header td {
text-align: left;
border-bottom: 1px solid #C0C0C0;
}
table.bitfields tr.header td.bits {
text-align: center;
}
table.enum tr.header td {
text-align: center;
border-top: none;
border-bottom: none;
}
table.enum tr.header2 td {
text-align: center;
}
table.bitfields td.bits, table.enum td.value, table.enum td.value2 {
font-weight: bold;
text-align: center;
}
table.enum td.value2 {
border-left: 1px solid #C0C0C0;
}
table.enum td.l {
text-align: center;
border-left: 1px solid #E0E0E0;
}
table.bitfields td p, table.enum td p {
margin: 0px;
padding: 3px 0px 0px 0px;
}
table.bitfields td p.name, table.bitfields td p span.name, table.enum td p.name {
font-weight: bold;
padding-top: 0px;
}
table.bitfields td p span.attr {
color: #606060;
padding-top: 0px;
}
table.extended_info {
border: 1px solid #D8D8D8;
border-collapse: collapse;
padding: 0px;
}
table.extended_info td.outercell {
border: 1px solid #D8D8D8;
padding: 0px;
}
p.reg_info, p.enum_info {
color: #606060;
margin: 0px;
padding: 5px 0px 0px 20px;
}
p.offset_info, td.offset_info {
text-align: left;
font-weight: bold;
margin: 0px;
/* top right bottom left*/
padding: 0px 0px 5px 0px;
color: #006060;
}
@media print {
p.reg_info, p.enum_info {
font-size: 70%;
color: black;
padding: 5px 0px 0px 15px;
}
}
/*Prism.js CSS*/
/* PrismJS 1.15.0
https://prismjs.com/download.html#themes=prism-twilight&languages=markup+css+clike+javascript+perl+python+tcl+verilog+vhdl */
/**
* prism.js Twilight theme
* Based (more or less) on the Twilight theme originally of Textmate fame.
* @author Remy Bach
*/
code[class*="language-"],
pre[class*="language-"] {
color: white;
background: none;
font-family: Consolas, Monaco, 'Andale Mono', 'Ubuntu Mono', monospace;
font-size: 1em;
text-align: left;
text-shadow: 0 -.1em .2em black;
white-space: pre;
word-spacing: normal;
word-break: normal;
word-wrap: normal;
line-height: 1.5;
-moz-tab-size: 4;
-o-tab-size: 4;
tab-size: 4;
-webkit-hyphens: none;
-moz-hyphens: none;
-ms-hyphens: none;
hyphens: none;
}
pre[class*="language-"],
:not(pre) > code[class*="language-"] {
background: hsl(0, 0%, 8%); /* #141414 */
}
/* Code blocks */
pre[class*="language-"] {
border-radius: .5em;
border: .3em solid hsl(0, 0%, 33%); /* #282A2B */
box-shadow: 1px 1px .5em black inset;
margin: .5em 0;
overflow: auto;
padding: 1em;
}
pre[class*="language-"]::-moz-selection {
/* Firefox */
background: hsl(200, 4%, 16%); /* #282A2B */
}
pre[class*="language-"]::selection {
/* Safari */
background: hsl(200, 4%, 16%); /* #282A2B */
}
/* Text Selection colour */
pre[class*="language-"]::-moz-selection, pre[class*="language-"] ::-moz-selection,
code[class*="language-"]::-moz-selection, code[class*="language-"] ::-moz-selection {
text-shadow: none;
background: hsla(0, 0%, 93%, 0.15); /* #EDEDED */
}
pre[class*="language-"]::selection, pre[class*="language-"] ::selection,
code[class*="language-"]::selection, code[class*="language-"] ::selection {
text-shadow: none;
background: hsla(0, 0%, 93%, 0.15); /* #EDEDED */
}
/* Inline code */
:not(pre) > code[class*="language-"] {
border-radius: .3em;
border: .13em solid hsl(0, 0%, 33%); /* #545454 */
box-shadow: 1px 1px .3em -.1em black inset;
padding: .15em .2em .05em;
white-space: normal;
}
.token.comment,
.token.prolog,
.token.doctype,
.token.cdata {
color: hsl(0, 0%, 47%); /* #777777 */
}
.token.punctuation {
opacity: .7;
}
.namespace {
opacity: .7;
}
.token.tag,
.token.boolean,
.token.number,
.token.deleted {
color: hsl(14, 58%, 55%); /* #CF6A4C */
}
.token.keyword,
.token.property,
.token.selector,
.token.constant,
.token.symbol,
.token.builtin {
color: hsl(53, 89%, 79%); /* #F9EE98 */
}
.token.attr-name,
.token.attr-value,
.token.string,
.token.char,
.token.operator,
.token.entity,
.token.url,
.language-css .token.string,
.style .token.string,
.token.variable,
.token.inserted {
color: hsl(76, 21%, 52%); /* #8F9D6A */
}
.token.atrule {
color: hsl(218, 22%, 55%); /* #7587A6 */
}
.token.regex,
.token.important {
color: hsl(42, 75%, 65%); /* #E9C062 */
}
.token.important,
.token.bold {
font-weight: bold;
}
.token.italic {
font-style: italic;
}
.token.entity {
cursor: help;
}
pre[data-line] {
padding: 1em 0 1em 3em;
position: relative;
}
/* Markup */
.language-markup .token.tag,
.language-markup .token.attr-name,
.language-markup .token.punctuation {
color: hsl(33, 33%, 52%); /* #AC885B */
}
/* Make the tokens sit above the line highlight so the colours don't look faded. */
.token {
position: relative;
z-index: 1;
}
.line-highlight {
background: hsla(0, 0%, 33%, 0.25); /* #545454 */
background: linear-gradient(to right, hsla(0, 0%, 33%, .1) 70%, hsla(0, 0%, 33%, 0)); /* #545454 */
border-bottom: 1px dashed hsl(0, 0%, 33%); /* #545454 */
border-top: 1px dashed hsl(0, 0%, 33%); /* #545454 */
left: 0;
line-height: inherit;
margin-top: 0.75em; /* Same as .prism’s padding-top */
padding: inherit 0;
pointer-events: none;
position: absolute;
right: 0;
white-space: pre;
z-index: 0;
}
.line-highlight:before,
.line-highlight[data-end]:after {
background-color: hsl(215, 15%, 59%); /* #8794A6 */
border-radius: 999px;
box-shadow: 0 1px white;
color: hsl(24, 20%, 95%); /* #F5F2F0 */
content: attr(data-start);
font: bold 65%/1.5 sans-serif;
left: .6em;
min-width: 1em;
padding: 0 .5em;
position: absolute;
text-align: center;
text-shadow: none;
top: .4em;
vertical-align: .3em;
}
.line-highlight[data-end]:after {
bottom: .4em;
content: attr(data-end);
top: auto;
}
/*Markdown Style*/
/* All info tags that were created within a markdown regmap or document
are in <div class="xmlpmd">. Use that specifier to provide style for
those sections. */
.xmlpmd table {
border-collapse: collapse;
border: 1px solid #C0C0C0;
}
.xmlpmd table thead tr th {
background-color: #F0F0F0;
color: #004080;
text-align: center;
border: 1px solid #C0C0C0;
}
.xmlpmd table tbody tr td {
border: 1px solid #C0C0C0;
padding: 5px
}
</style>
<script type="text/javascript">
function toggleText( id, sign ) {
if (sign == "nochange") return;
if ( document.getElementById )
elem = document.getElementById( id );
else if ( document.all )
elem = eval( "document.all." + id );
if (elem) {
elemStyle = elem.style;
if (sign=="+") {
elemStyle.display = "block"
} else {
elemStyle.display = "none"
}
/*if ( elemStyle.display == "block" ) {
elemStyle.display = "none"
} else {
elemStyle.display = "block"
}*/
}
}
function changeSh( id ) {
if ( document.getElementById )
elem = document.getElementById( id );
else if ( document.all )
elem = eval( "document.all." + id );
else
return "nochange";
val = "-";
if (elem.innerHTML == "show here") {
val = "+";
elem.innerHTML = "hide";
} else {
elem.innerHTML = "show here";
}
return val;
}
function sb( id ) {
var sign = changeSh("show_" + id);
toggleText("div_" + id, sign);
}
function changeSh2( id ) {
if ( document.getElementById )
elem = document.getElementById( id );
else if ( document.all )
elem = eval( "document.all." + id );
else
return "nochange";
val = "-";
if (elem.innerHTML == "show") {
val = "+";
elem.innerHTML = "hide";
} else {
elem.innerHTML = "show";
}
return val;
}
function sa( id ) {
var sign = changeSh2("show_" + id);
toggleText("div_" + id, sign);
}
</script>
<script type="text/javascript">//Prism.js//
/* PrismJS 1.15.0
https://prismjs.com/download.html#themes=prism-twilight&languages=markup+css+clike+javascript+perl+python+tcl+verilog+vhdl */
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</script>
</head><body>
<div class="regmap">
<a name="X4XX_FPGA"></a>
<h1 class="regmap">X4XX_FPGA</h1>
This documentation provides a description of the different register spaces available
for the USRP X4xx Open-Source FPGA target implementation, accessible through the
embedded ARM A53 processor in the RFSoC chip, and other UHD hosts.
<p>The top is defined in HDL source file common_regs.v, x4xx.v.</p>
<div class="group"><a name="P5 Content"></a><h2 class="group">P5 Content</h2>
<div class="register"><h3 class="register">Register map supplied for open-source projects</h3>
<i><BR/><BR/>"All content provided is Copyright 2022 National Instruments Corporation.
For information on NI trademark guidelines, please see <a href="http://www.ni.com/legal/trademarks/">http://www.ni.com/legal/trademarks/</a>. For the NI Patent Notice, please see <a href="http://www.ni.com/legal/patents/">http://www.ni.com/legal/patents/</a>."
</i></div><BR/>
</div>
<div class="group"><a name="ports"></a><h2 class="group">ports</h2>
This section lists all common Processing System ports through
which the register maps in this project are accessed. Each input
port to the fabric will point to a regmap.
<div class="register">
<a name="X4XX_FPGA|ARM_M_AXI_HPM0"></a>
<h3 class="register">Port ARM_M_AXI_HPM0 (input)</h3>
<p class="offset_info">
Target Regmap = <a href="#AXI_HPM0_REGMAP">AXI_HPM0_REGMAP</a>
</p>
<div class="info">
This is the main AXI4-Lite master interface that the PS
exposes to the kernel to interact with the FPGA fabric.
There are multiple endpoints connected to this interface.
</div>
<p class="reg_info">
This port is defined in HDL source file common_regs.v.
</p>
</div>
<div class="register">
<a name="X4XX_FPGA|ARM_S_AXI_HPC0"></a>
<h3 class="register">Port ARM_S_AXI_HPC0 (output)</h3>
<p class="offset_info">
Source Window = <a href="#PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW">PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW</a>
</p>
<div class="info">
This is one of the two cache-coherent AXI slave ports available to
communicate from the fabric (master) to the PS (slave).
</div>
<p class="reg_info">
This port is defined in HDL source file common_regs.v.
</p>
</div>
<div class="register">
<a name="X4XX_FPGA|ARM_S_AXI_HPC1"></a>
<h3 class="register">Port ARM_S_AXI_HPC1 (output)</h3>
<p class="offset_info">
Source Window = <a href="#PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW">PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW</a>
</p>
<div class="info">
This is one of the two cache-coherent AXI slave ports available to
communicate from the fabric (master) to the PS (slave).
</div>
<p class="reg_info">
This port is defined in HDL source file common_regs.v.
</p>
</div>
<div class="register">
<a name="X4XX_FPGA|ARM_SPI1_CS3"></a>
<h3 class="register">Port ARM_SPI1_CS3 (input)</h3>
<p class="offset_info">
Target Regmap = <a href="#MB_CPLD_PS_REGMAP">MB_CPLD_PS_REGMAP</a>
</p>
<div class="info">
This is the SPI1 interface
(see <a href="https://www.xilinx.com/html_docs/registers/ug1087/mod___spi.html" target="_blank">Zynq UltraScale+ Devices Register Reference</a>)
of the PS.
With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.<br>
The request format on SPI is defined as.<br>
<b>Write request:</b>
<ul>
<li>1'b1 = write
<li>15 bit address
<li>32 bit data (MOSI)
<li>8 bit processing gap
<li>5 bit padding
<li>1 bit ack
<li>2 bit status
</ul>
<b>Read request:</b>
<ul>
<li>1'b0 = read
<li>15 bit address
<li>8 bit processing gap
<li>32 bit data (MISO)
<li>5 bit padding
<li>1 bit ack
<li>2 bit status
</ul>
</div>
<p class="reg_info">
This port is defined in HDL source file common_regs.v.
</p>
</div>
</div>
</div>
<div class="regmap">
<a name="AXI_HPM0_REGMAP"></a>
<h1 class="regmap">AXI_HPM0_REGMAP</h1>
<div class="xmlpmd">
<p>This is the map for the register space that the Processing System's
M_AXI_HPM0_FPD port (AXI4 master interface) has access to.
This port has a 40-bit address bus.</p></div>
<div class="group"><a name="AXI_HPM0_REGMAP|COMMON"></a><h2 class="group">COMMON</h2>
<div class="xmlpmd">
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|RPU"></a>
<h3 class="register">Offset 0x80000000: RPU Window (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|RPU_in')">(<span id="show_AXI_HPM0_REGMAP|RPU_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|RPU_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RPU</td></tr>
<tr><td class="offset_info" align="right"> offset=0x80000000</td></tr>
<tr><td class="offset_info" align="right"> size=0x10000 (64 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x80000000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Space reserved for RPU access</p></div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|JTAG_ENGINE"></a>
<h3 class="register">Offset 0x1000000000: JTAG_ENGINE Window (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|JTAG_ENGINE_in')">(<span id="show_AXI_HPM0_REGMAP|JTAG_ENGINE_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|JTAG_ENGINE_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">JTAG_ENGINE</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1000000000</td></tr>
<tr><td class="offset_info" align="right"> size=0x1000 (4 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000000000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Register space for the JTAG engine for MB CPLD programming.</p></div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|RESERVED"></a>
<h3 class="register">Offset 0x100003F000: RESERVED Window (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|RESERVED_in')">(<span id="show_AXI_HPM0_REGMAP|RESERVED_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|RESERVED_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RESERVED</td></tr>
<tr><td class="offset_info" align="right"> offset=0x100003F000</td></tr>
<tr><td class="offset_info" align="right"> size=0x1000 (4 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x100003F000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Register space reserved for future use.</p></div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|MPM_ENDPOINT"></a>
<h3 class="register">Offset 0x1000080000: MPM_ENDPOINT Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#PL_CPLD_REGMAP">PL_CPLD_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|MPM_ENDPOINT_in')">(<span id="show_AXI_HPM0_REGMAP|MPM_ENDPOINT_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|MPM_ENDPOINT_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">MPM_ENDPOINT</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1000080000</td></tr>
<tr><td class="offset_info" align="right"> size=0x20000 (128 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000080000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>MPM endpoint fro MB/DB communication.</p></div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|CORE_REGS"></a>
<h3 class="register">Offset 0x10000A0000: CORE_REGS Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#CORE_REGS_REGMAP">CORE_REGS_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|CORE_REGS_in')">(<span id="show_AXI_HPM0_REGMAP|CORE_REGS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|CORE_REGS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CORE_REGS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x10000A0000</td></tr>
<tr><td class="offset_info" align="right"> size=0x4000 (16 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Register space reserved for mboard-regs (Core).</p></div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|INT_ETH_DMA"></a>
<h3 class="register">Offset 0x10000A4000: INT_ETH_DMA Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#ETH_DMA_CTRL_REGMAP">ETH_DMA_CTRL_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|INT_ETH_DMA_in')">(<span id="show_AXI_HPM0_REGMAP|INT_ETH_DMA_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|INT_ETH_DMA_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">INT_ETH_DMA</td></tr>
<tr><td class="offset_info" align="right"> offset=0x10000A4000</td></tr>
<tr><td class="offset_info" align="right"> size=0x6000 (24 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A4000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>AXI DMA engine for internal Ethernet interface.</p></div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|INT_ETH_REGS"></a>
<h3 class="register">Offset 0x10000AA000: INT_ETH_REGS Window (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|INT_ETH_REGS_in')">(<span id="show_AXI_HPM0_REGMAP|INT_ETH_REGS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|INT_ETH_REGS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">INT_ETH_REGS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x10000AA000</td></tr>
<tr><td class="offset_info" align="right"> size=0x2000 (8 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000AA000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Misc. registers for internal Ethernet.</p></div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|RFDC"></a>
<h3 class="register">Offset 0x1000100000: RFDC Window (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|RFDC_in')">(<span id="show_AXI_HPM0_REGMAP|RFDC_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|RFDC_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RFDC</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1000100000</td></tr>
<tr><td class="offset_info" align="right"> size=0x40000 (256 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000100000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Register space occupied by the Xilinx RFDC IP block.</p></div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|RFDC_REGS"></a>
<h3 class="register">Offset 0x1000140000: RFDC_REGS Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#RFDC_REGS_REGMAP">RFDC_REGS_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|RFDC_REGS_in')">(<span id="show_AXI_HPM0_REGMAP|RFDC_REGS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|RFDC_REGS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RFDC_REGS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1000140000</td></tr>
<tr><td class="offset_info" align="right"> size=0x20000 (128 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000140000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Register space for RFDC control/status registers.</p></div>
</div>
</div>
</div>
<div class="group"><a name="AXI_HPM0_REGMAP|UHD_ONLY"></a><h2 class="group">UHD_ONLY</h2>
<div class="xmlpmd">
<ul>
<li>0_0 indicates QSFP0 - Lane0 or a 4 LANE QSFP0</li>
<li>0_1 indicates QSFP0 - Lane1</li>
<li>0_2 indicates QSFP0 - Lane2</li>
<li>0_3 indicates QSFP0 - Lane3</li>
<li>1_0 indicates QSFP1 - Lane0 or a 4 LANE QSFP1</li>
<li>1_1 indicates QSFP1 - Lane1</li>
<li>1_2 indicates QSFP1 - Lane2</li>
<li>1_3 indicates QSFP1 - Lane3</li>
</ul></div>
<div class="register">
<a name="AXI_HPM0_REGMAP|QSFP_0_0"></a>
<h3 class="register">Offset 0x1200000000: QSFP_0_0 Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#QSFP_REGMAP">QSFP_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|QSFP_0_0_in')">(<span id="show_AXI_HPM0_REGMAP|QSFP_0_0_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|QSFP_0_0_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_0_0</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1200000000</td></tr>
<tr><td class="offset_info" align="right"> size=0x10000 (64 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200000000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|QSFP_0_1"></a>
<h3 class="register">Offset 0x1200010000: QSFP_0_1 Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#QSFP_REGMAP">QSFP_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|QSFP_0_1_in')">(<span id="show_AXI_HPM0_REGMAP|QSFP_0_1_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|QSFP_0_1_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_0_1</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1200010000</td></tr>
<tr><td class="offset_info" align="right"> size=0x10000 (64 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200010000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|QSFP_0_2"></a>
<h3 class="register">Offset 0x1200020000: QSFP_0_2 Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#QSFP_REGMAP">QSFP_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|QSFP_0_2_in')">(<span id="show_AXI_HPM0_REGMAP|QSFP_0_2_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|QSFP_0_2_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_0_2</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1200020000</td></tr>
<tr><td class="offset_info" align="right"> size=0x10000 (64 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200020000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|QSFP_0_3"></a>
<h3 class="register">Offset 0x1200030000: QSFP_0_3 Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#QSFP_REGMAP">QSFP_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|QSFP_0_3_in')">(<span id="show_AXI_HPM0_REGMAP|QSFP_0_3_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|QSFP_0_3_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_0_3</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1200030000</td></tr>
<tr><td class="offset_info" align="right"> size=0x10000 (64 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200030000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|QSFP_1_0"></a>
<h3 class="register">Offset 0x1200040000: QSFP_1_0 Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#QSFP_REGMAP">QSFP_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|QSFP_1_0_in')">(<span id="show_AXI_HPM0_REGMAP|QSFP_1_0_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|QSFP_1_0_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_1_0</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1200040000</td></tr>
<tr><td class="offset_info" align="right"> size=0x10000 (64 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200040000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|QSFP_1_1"></a>
<h3 class="register">Offset 0x1200050000: QSFP_1_1 Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#QSFP_REGMAP">QSFP_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|QSFP_1_1_in')">(<span id="show_AXI_HPM0_REGMAP|QSFP_1_1_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|QSFP_1_1_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_1_1</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1200050000</td></tr>
<tr><td class="offset_info" align="right"> size=0x10000 (64 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200050000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|QSFP_1_2"></a>
<h3 class="register">Offset 0x1200060000: QSFP_1_2 Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#QSFP_REGMAP">QSFP_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|QSFP_1_2_in')">(<span id="show_AXI_HPM0_REGMAP|QSFP_1_2_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|QSFP_1_2_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_1_2</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1200060000</td></tr>
<tr><td class="offset_info" align="right"> size=0x10000 (64 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200060000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
<div class="register">
<a name="AXI_HPM0_REGMAP|QSFP_1_3"></a>
<h3 class="register">Offset 0x1200070000: QSFP_1_3 Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#QSFP_REGMAP">QSFP_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('AXI_HPM0_REGMAP|QSFP_1_3_in')">(<span id="show_AXI_HPM0_REGMAP|QSFP_1_3_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_AXI_HPM0_REGMAP|QSFP_1_3_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_1_3</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1200070000</td></tr>
<tr><td class="offset_info" align="right"> size=0x10000 (64 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200070000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
</div>
</div>
<div class="regmap">
<a name="MB_CPLD_PS_REGMAP"></a>
<h1 class="regmap">MB_CPLD_PS_REGMAP</h1>
<div class="xmlpmd">
<p>This register map is available using the PS CPLD SPI interface.</p></div>
<div class="group"><a name="MB_CPLD_PS_REGMAP|MB_CPLD_PS_WINDOWS"></a><h2 class="group">MB_CPLD_PS_WINDOWS</h2>
<div class="xmlpmd">
</div>
<div class="register">
<a name="MB_CPLD_PS_REGMAP|PS_REGISTERS"></a>
<h3 class="register">Offset 0x0000: PS_REGISTERS Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#PS_CPLD_BASE_REGMAP">PS_CPLD_BASE_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('MB_CPLD_PS_REGMAP|PS_REGISTERS_in')">(<span id="show_MB_CPLD_PS_REGMAP|PS_REGISTERS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_MB_CPLD_PS_REGMAP|PS_REGISTERS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">PS_REGISTERS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
<tr><td class="offset_info" align="right"> size=0x40 (64 bytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file mb_cpld.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
<div class="register">
<a name="MB_CPLD_PS_REGMAP|RECONFIG"></a>
<h3 class="register">Offset 0x0040: RECONFIG Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#RECONFIG_REGMAP">RECONFIG_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('MB_CPLD_PS_REGMAP|RECONFIG_in')">(<span id="show_MB_CPLD_PS_REGMAP|RECONFIG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_MB_CPLD_PS_REGMAP|RECONFIG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RECONFIG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0040</td></tr>
<tr><td class="offset_info" align="right"> size=0x20 (32 bytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000040
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file mb_cpld.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
<div class="register">
<a name="MB_CPLD_PS_REGMAP|POWER_REGISTERS"></a>
<h3 class="register">Offset 0x0060: POWER_REGISTERS Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#PS_POWER_REGMAP">PS_POWER_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('MB_CPLD_PS_REGMAP|POWER_REGISTERS_in')">(<span id="show_MB_CPLD_PS_REGMAP|POWER_REGISTERS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_MB_CPLD_PS_REGMAP|POWER_REGISTERS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">POWER_REGISTERS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0060</td></tr>
<tr><td class="offset_info" align="right"> size=0x20 (32 bytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000060
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file mb_cpld.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
</div>
<div class="group"><a name="MB_CPLD_PS_REGMAP|PS_SPI_ENDPOINTS"></a><h2 class="group">PS_SPI_ENDPOINTS</h2>
<div class="xmlpmd">
</div>
<div class="enum">
<a name="MB_CPLD_PS_REGMAP|SPI_ENDPOINT"></a>
<h3 class="enum">SPI_ENDPOINT Enumeration</h3>
<div class="xmlpmd">
</div>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' > Value </td>
<td class="l" colspan='1'> Name </td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='MB_CPLD_PS_REGMAP|SPI_ENDPOINT|PS_CS_MB_CPLD'></a>PS_CS_MB_CPLD</p>
<p class="l"><div class="xmlpmd">
</div>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='MB_CPLD_PS_REGMAP|SPI_ENDPOINT|PS_CS_LMK32'></a>PS_CS_LMK32</p>
<p class="l"><div class="xmlpmd">
</div>
</td>
</tr>
<tr valign="top">
<td class='value'>2</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='MB_CPLD_PS_REGMAP|SPI_ENDPOINT|PS_CS_TPM'></a>PS_CS_TPM</p>
<p class="l"><div class="xmlpmd">
</div>
</td>
</tr>
<tr valign="top">
<td class='value'>3</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='MB_CPLD_PS_REGMAP|SPI_ENDPOINT|PS_CS_PHASE_DAC'></a>PS_CS_PHASE_DAC</p>
<p class="l"><div class="xmlpmd">
</div>
</td>
</tr>
<tr valign="top">
<td class='value'>4</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='MB_CPLD_PS_REGMAP|SPI_ENDPOINT|PS_CS_DB0_CAL_EEPROM'></a>PS_CS_DB0_CAL_EEPROM</p>
<p class="l"><div class="xmlpmd">
</div>
</td>
</tr>
<tr valign="top">
<td class='value'>5</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='MB_CPLD_PS_REGMAP|SPI_ENDPOINT|PS_CS_DB1_CAL_EEPROM'></a>PS_CS_DB1_CAL_EEPROM</p>
<p class="l"><div class="xmlpmd">
</div>
</td>
</tr>
<tr valign="top">
<td class='value'>6</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='MB_CPLD_PS_REGMAP|SPI_ENDPOINT|PS_CS_CLK_AUX_DB'></a>PS_CS_CLK_AUX_DB</p>
<p class="l"><div class="xmlpmd">
</div>
</td>
</tr>
<tr valign="top">
<td class='value'>7</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='MB_CPLD_PS_REGMAP|SPI_ENDPOINT|PS_CS_IDLE'></a>PS_CS_IDLE</p>
<p class="l"><div class="xmlpmd">
</div>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file mb_cpld.v.
</p>
</div>
</div>
</div>
<div class="regmap">
<a name="CMAC_REGMAP"></a>
<h1 class="regmap">CMAC_REGMAP</h1>
<div class="xmlpmd">
</div>
<div class="group"><a name="CMAC_REGMAP|XILINX_CMAC_REGISTERS"></a><h2 class="group">XILINX_CMAC_REGISTERS</h2>
<div class="xmlpmd">
<p>100G MAC ethernet registers (Link 0) defined in the CMAC Manual starting on pg 187.</p>
<ul>
<li>http://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf</li>
</ul></div>
</div>
</div>
<div class="regmap">
<a name="CONSTANTS_REGMAP"></a>
<h1 class="regmap">CONSTANTS_REGMAP</h1>
<div class="group"><a name="CONSTANTS_REGMAP|CONSTANTS_GROUP"></a><h2 class="group">CONSTANTS_GROUP</h2>
Basic registers containing version and capabilities information.
<div class="enum">
<a name="CONSTANTS_REGMAP|CONSTANTS_ENUM"></a>
<h3 class="enum">CONSTANTS_ENUM Enumeration</h3>
This enumeration is used to create the constants held in the basic registers.
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' colspan='2'> Value </td>
<td class="l" rowspan='2' colspan='1'> Name </td>
</tr>
<tr class="header2" valign="bottom">
<td class='value'> Dec </td>
<td class='l'> Hex </td>
</tr>
<tr valign="top">
<td class='value'>173157671</td>
<td class='l'>0x0A522D27</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='CONSTANTS_REGMAP|CONSTANTS_ENUM|PS_CPLD_SIGNATURE'></a>PS_CPLD_SIGNATURE</p>
</td>
</tr>
<tr valign="top">
<td class='value'>538059028</td>
<td class='l'>0x20122114</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='CONSTANTS_REGMAP|CONSTANTS_ENUM|OLDEST_CPLD_REVISION'></a>OLDEST_CPLD_REVISION</p>
</td>
</tr>
<tr valign="top">
<td class='value'>554767893</td>
<td class='l'>0x21111615</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='CONSTANTS_REGMAP|CONSTANTS_ENUM|CPLD_REVISION'></a>CPLD_REVISION</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1071406151</td>
<td class='l'>0x3FDC5C47</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='CONSTANTS_REGMAP|CONSTANTS_ENUM|PL_CPLD_SIGNATURE'></a>PL_CPLD_SIGNATURE</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file mb_cpld.v.
</p>
</div>
</div>
</div>
<div class="regmap">
<a name="CORE_REGS_REGMAP"></a>
<h1 class="regmap">CORE_REGS_REGMAP</h1>
This is the map for the registers that the CORE_REGS window has access to
from the ARM_AXI_HPM0_FPD port.
The registers contained here conform the mboard-regs node that MPM uses
to manage general FPGA control/status calls, such as versioning,
timekeeper, GPIO, etc.
The following diagram shows how the communication bus interacts with the
modules in CORE_REGS.
<img src = "x4xx_core_common_buses.svg"
<div class="group"><a name="CORE_REGS_REGMAP|CORE_REGS"></a><h2 class="group">CORE_REGS</h2>
<div class="register">
<a name="CORE_REGS_REGMAP|GLOBAL_REGS"></a>
<h3 class="register">Offset 0x0000: GLOBAL_REGS Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#GLOBAL_REGS_REGMAP">GLOBAL_REGS_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('CORE_REGS_REGMAP|GLOBAL_REGS_in')">(<span id="show_CORE_REGS_REGMAP|GLOBAL_REGS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_CORE_REGS_REGMAP|GLOBAL_REGS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">GLOBAL_REGS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
<tr><td class="offset_info" align="right"> size=0xC00 (3 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
<div class="info">
Window to access global registers in the FPGA.
</div>
</div>
<div class="register">
<a name="CORE_REGS_REGMAP|VERSIONING_REGS"></a>
<h3 class="register">Offset 0x0C00: VERSIONING_REGS Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#VERSIONING_REGS_REGMAP">VERSIONING_REGS_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('CORE_REGS_REGMAP|VERSIONING_REGS_in')">(<span id="show_CORE_REGS_REGMAP|VERSIONING_REGS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_CORE_REGS_REGMAP|VERSIONING_REGS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">VERSIONING_REGS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0C00</td></tr>
<tr><td class="offset_info" align="right"> size=0x400 (1 Kbyte)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0C00
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
<div class="info">
Window to access versioning registers in the FPGA.
</div>
</div>
<div class="register">
<a name="CORE_REGS_REGMAP|TIMEKEEPER"></a>
<h3 class="register">Offset 0x1000: TIMEKEEPER Window (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('CORE_REGS_REGMAP|TIMEKEEPER_in')">(<span id="show_CORE_REGS_REGMAP|TIMEKEEPER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_CORE_REGS_REGMAP|TIMEKEEPER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">TIMEKEEPER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1000</td></tr>
<tr><td class="offset_info" align="right"> size=0x20 (32 bytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A1000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
<div class="info">
Window to access the timekeeper register map.
</div>
</div>
<div class="register">
<a name="CORE_REGS_REGMAP|DIO"></a>
<h3 class="register">Offset 0x2000: DIO Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#DIO_REGMAP">DIO_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('CORE_REGS_REGMAP|DIO_in')">(<span id="show_CORE_REGS_REGMAP|DIO_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_CORE_REGS_REGMAP|DIO_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO</td></tr>
<tr><td class="offset_info" align="right"> offset=0x2000</td></tr>
<tr><td class="offset_info" align="right"> size=0x40 (64 bytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A2000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
<div class="info">
Window to access the DIO register map.
</div>
</div>
</div>
</div>
<div class="regmap">
<a name="CPLD_INTERFACE_REGMAP"></a>
<h1 class="regmap">CPLD_INTERFACE_REGMAP</h1>
<div class="group"><a name="CPLD_INTERFACE_REGMAP|CPLD_INTERFACE_REGS"></a><h2 class="group">CPLD_INTERFACE_REGS</h2>
Basic registers containing version and capabilities information.
<div class="register">
<a name="CPLD_INTERFACE_REGMAP|SIGNATURE_REGISTER"></a>
<h3 class="register">Offset 0x0000: SIGNATURE_REGISTER Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('CPLD_INTERFACE_REGMAP|SIGNATURE_REGISTER_in')">(<span id="show_CPLD_INTERFACE_REGMAP|SIGNATURE_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_CPLD_INTERFACE_REGMAP|SIGNATURE_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|BASE">PL_CPLD_REGMAP|BASE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SIGNATURE_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000080000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file cpld_interface_regs.v.</p>
</div>
<div class="info">
Contains the product's signature.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..0</td>
<td>
<p><span class="name"><a name="CPLD_INTERFACE_REGMAP|SIGNATURE_REGISTER|PRODUCT_SIGNATURE"></a>PRODUCT_SIGNATURE</span><span class="attr"> </span></p>
<p>fixed value 0xCB1D1FAC</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="CPLD_INTERFACE_REGMAP|SCRATCH_REGISTER"></a>
<h3 class="register">Offset 0x000C: SCRATCH_REGISTER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('CPLD_INTERFACE_REGMAP|SCRATCH_REGISTER_in')">(<span id="show_CPLD_INTERFACE_REGMAP|SCRATCH_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_CPLD_INTERFACE_REGMAP|SCRATCH_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|BASE">PL_CPLD_REGMAP|BASE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SCRATCH_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x000C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x100008000C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file cpld_interface_regs.v.</p>
</div>
<div class="info">
Read/write register for general software use.
</div>
</div>
</div>
<div class="group"><a name="CPLD_INTERFACE_REGMAP|CPLD_SPI_CONTROL_REGS"></a><h2 class="group">CPLD_SPI_CONTROL_REGS</h2>
Registers to control the SPI clock frequency of the CPLD interfaces.
The resulting clock frequency is calculated by <math><mrow><mfrac><mrow><msub><mi>f</mi><mrow><mi>PRC</mi></mrow></msub></mrow><mrow><mn>2</mn><mrow><mo form="prefix">(</mo><mo>divider</mi><mo>+</mo><mn>1</mn><mo form="postfix">)</mo></mrow></mrow></mfrac></mrow></math>.
<br>
Note that the PLL Reference Clock (PRC) is depending on the RF clocks.
<div class="register">
<a name="CPLD_INTERFACE_REGMAP|MOTHERBOARD_CPLD_DIVIDER"></a>
<h3 class="register">Offset 0x0020: MOTHERBOARD_CPLD_DIVIDER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('CPLD_INTERFACE_REGMAP|MOTHERBOARD_CPLD_DIVIDER_in')">(<span id="show_CPLD_INTERFACE_REGMAP|MOTHERBOARD_CPLD_DIVIDER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_CPLD_INTERFACE_REGMAP|MOTHERBOARD_CPLD_DIVIDER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|BASE">PL_CPLD_REGMAP|BASE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">MOTHERBOARD_CPLD_DIVIDER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0020</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000080020
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000002
</p>
<p class="reg_info">This register is defined in HDL source file cpld_interface_regs.v.</p>
</div>
<div class="info">
Clock divider used for SPI transactions targeting the MB CPLD.<br/>
Minimum required value is 2.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..0</td>
<td>
<p><span class="name"><a name="CPLD_INTERFACE_REGMAP|MOTHERBOARD_CPLD_DIVIDER|MB_DIVIDER"></a>MB_DIVIDER</span><span class="attr"> (initialvalue=2)</span></p>
<p>Divider value</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="CPLD_INTERFACE_REGMAP|DAUGHTERBOARD_CPLD_DIVIDER"></a>
<h3 class="register">Offset 0x0024: DAUGHTERBOARD_CPLD_DIVIDER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('CPLD_INTERFACE_REGMAP|DAUGHTERBOARD_CPLD_DIVIDER_in')">(<span id="show_CPLD_INTERFACE_REGMAP|DAUGHTERBOARD_CPLD_DIVIDER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_CPLD_INTERFACE_REGMAP|DAUGHTERBOARD_CPLD_DIVIDER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|BASE">PL_CPLD_REGMAP|BASE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DAUGHTERBOARD_CPLD_DIVIDER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0024</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000080024
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000005
</p>
<p class="reg_info">This register is defined in HDL source file cpld_interface_regs.v.</p>
</div>
<div class="info">
Clock divider used for SPI transactions targeting any of the DB CPLDs.<br/>
Minimum required value is 5.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..0</td>
<td>
<p><span class="name"><a name="CPLD_INTERFACE_REGMAP|DAUGHTERBOARD_CPLD_DIVIDER|DB_DIVIDER"></a>DB_DIVIDER</span><span class="attr"> (initialvalue=5)</span></p>
<p>Divider value</p>
</td>
</tr>
</table>
</div>
</div>
<div class="group"><a name="CPLD_INTERFACE_REGMAP|IPASS_REGS"></a><h2 class="group">IPASS_REGS</h2>
<div class="register">
<a name="CPLD_INTERFACE_REGMAP|IPASS_CONTROL"></a>
<h3 class="register">Offset 0x0010: IPASS_CONTROL Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('CPLD_INTERFACE_REGMAP|IPASS_CONTROL_in')">(<span id="show_CPLD_INTERFACE_REGMAP|IPASS_CONTROL_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_CPLD_INTERFACE_REGMAP|IPASS_CONTROL_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|BASE">PL_CPLD_REGMAP|BASE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">IPASS_CONTROL</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0010</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000080010
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file cpld_interface_regs.v.</p>
</div>
<div class="info">
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..1</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="CPLD_INTERFACE_REGMAP|IPASS_CONTROL|IPASS_ENABLE_TRANSFER"></a>IPASS_ENABLE_TRANSFER</span><span class="attr"> </span></p>
<p>If 1 enables the forwarding of iPass cable present signal to MB CPLD
using ctrlport requests. On change from 0 to 1 the current status is
transferred to the MB CPLD via SPI ctrlport request initially.</p>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="regmap">
<a name="DIG_IFC_REGMAP"></a>
<h1 class="regmap">DIG_IFC_REGMAP</h1>
<div class="group"><a name="DIG_IFC_REGMAP|SPI_OVER_GPIO_REGS"></a><h2 class="group">SPI_OVER_GPIO_REGS</h2>
<div class="register">
<a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG"></a>
<h3 class="register">Offset 0x0000: SPI_SLAVE_CONFIG(3:0) Register Array (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('DIG_IFC_REGMAP|SPI_SLAVE_CONFIG_in')">(<span id="show_DIG_IFC_REGMAP|SPI_SLAVE_CONFIG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIG_IFC_REGMAP|SPI_SLAVE_CONFIG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIGITAL_IFC_REGS">RADIO_DIO_REGMAP|DIGITAL_IFC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SPI_SLAVE_CONFIG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000 + i*4</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00E000 + i*4
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info"><B>Initial Values</B><BR/>
<table>
<tr><td>default</td><td>=></td><td>0x00000000</td></tr>
</table>
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_spi.v.<BR/>
It uses RegType <b>SPI_SETUP</b> which is defined in HDL source file x4xx_gpio_spi.v.</p>
</div>
<div class="info">
Controls SPI Transaction<BR/>
Set of configuration registers for the supported slaves.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|MOSI_EDGE"></a>MOSI_EDGE</span><span class="attr"> (initialvalue=0)</span></p>
<p>Controls the edge in which the MOSI line is updated.</br>
0 = falling edge of SCLK.</br>
1 = rising edge of SCLK.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">26</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|MISO_EDGE"></a>MISO_EDGE</span><span class="attr"> (initialvalue=0)</span></p>
<p>Controls the edge in which the MISO line is latched.</br>
0 = falling edge of SCLK.</br>
1 = rising edge of SCLK.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">25..20</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|SPI_LENGTH"></a>SPI_LENGTH</span><span class="attr"> (initialvalue=0)</span></p>
<p>Indicates the length of SPI transactions to this slave.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">19..15</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|SLAVE_CS"></a>SLAVE_CS</span><span class="attr"> (initialvalue=0)</span></p>
<p>Indicates which GPIO line to use for the CS signal.</br>
0-11 : Port A GPIO</br>
16-27: Port B GPIO</p>
</td>
</tr>
<tr valign="top">
<td class="bits">14..10</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|SLAVE_MISO"></a>SLAVE_MISO</span><span class="attr"> (initialvalue=0)</span></p>
<p>Indicates which GPIO line to use for the MISO signal.</br>
0-11 : Port A GPIO</br>
16-27: Port B GPIO</p>
</td>
</tr>
<tr valign="top">
<td class="bits">9..5</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|SLAVE_MOSI"></a>SLAVE_MOSI</span><span class="attr"> (initialvalue=0)</span></p>
<p>Indicates which GPIO line to use for the MOSI signal.</br>
0-11 : Port A GPIO</br>
16-27: Port B GPIO</p>
</td>
</tr>
<tr valign="top">
<td class="bits">4..0</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|SLAVE_CLK"></a>SLAVE_CLK</span><span class="attr"> (initialvalue=0)</span></p>
<p>Indicates which GPIO line to use for the SCLK signal.</br>
0-11 : Port A GPIO</br>
16-27: Port B GPIO</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG"></a>
<h3 class="register">Offset 0x0010: SPI_TRANSACTION_CONFIG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG_in')">(<span id="show_DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIGITAL_IFC_REGS">RADIO_DIO_REGMAP|DIGITAL_IFC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SPI_TRANSACTION_CONFIG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0010</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00E010
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_spi.v.</p>
</div>
<div class="info">
Controls clock rate and target for subsequent SPI transactions.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..18</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">17..16</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG|SPI_SLAVE_SELECT"></a>SPI_SLAVE_SELECT</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..0</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG|SPI_CLK_DIV"></a>SPI_CLK_DIV</span><span class="attr"> (initialvalue=0)</span></p>
<p>Controls the rate for subsequent SPI transactions. SCLK = DataClk/[(SPI_CLK_DIV+1)]</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIG_IFC_REGMAP|SPI_TRANSACTION_GO"></a>
<h3 class="register">Offset 0x0014: SPI_TRANSACTION_GO Register (W)</h3>
<a class="sh_addrs" href="javascript:sa('DIG_IFC_REGMAP|SPI_TRANSACTION_GO_in')">(<span id="show_DIG_IFC_REGMAP|SPI_TRANSACTION_GO_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIG_IFC_REGMAP|SPI_TRANSACTION_GO_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIGITAL_IFC_REGS">RADIO_DIO_REGMAP|DIGITAL_IFC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SPI_TRANSACTION_GO</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0014</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00E014
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_spi.v.</p>
</div>
<div class="info">
Starts a SPI transaction
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..0w</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_TRANSACTION_GO|SPI_DATA"></a>SPI_DATA</span><span class="attr"> (initialvalue=0)</span></p>
<p>Payload to be sent for the SPI transaction. If the payload is shorter than 32 bits,
it must be aligned to the MSbs in this field. LSbs are ignored in this scenario.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIG_IFC_REGMAP|SPI_STATUS"></a>
<h3 class="register">Offset 0x0018: SPI_STATUS Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('DIG_IFC_REGMAP|SPI_STATUS_in')">(<span id="show_DIG_IFC_REGMAP|SPI_STATUS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIG_IFC_REGMAP|SPI_STATUS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIGITAL_IFC_REGS">RADIO_DIO_REGMAP|DIGITAL_IFC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SPI_STATUS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0018</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00E018
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_spi.v.</p>
</div>
<div class="info">
Contains the status of the SPI engine.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..25</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">24</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_STATUS|SPI_READY"></a>SPI_READY</span><span class="attr"> (initialvalue=0)</span></p>
<p>Indicates the SPI engine is ready to start a new SPI transaction.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..0</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_STATUS|SPI_RESPONSE"></a>SPI_RESPONSE</span><span class="attr"> (initialvalue=0)</span></p>
<p>Records the response of the last completed SPI transaction.</p>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="regmap">
<a name="DIO_REGMAP"></a>
<h1 class="regmap">DIO_REGMAP</h1>
<div class="group"><a name="DIO_REGMAP|DIO_REGS"></a><h2 class="group">DIO_REGS</h2>
Registers to control the GPIO buffer direction on the FPGA connected to
the DIO board. Further registers enable different sources to control and
read the GPIO lines as master. The following diagram shows how source
selection multiplexers are arranged, as well as an indicator for the
register that control them. </br>
<img src = "..\..\..\..\..\host\docs\res\x4xx_dio_source_muxes.svg"
alt="Front-Panel Programmable GPIOs"/></br>
Make sure the GPIO lines between FPGA and GPIO board are not driven by
two drivers. Set the DIO registers in <a href="#PS_CPLD_BASE_REGMAP">PS_CPLD_BASE_REGMAP</a> appropriately.
<div class="register">
<a name="DIO_REGMAP|DIO_MASTER_REGISTER"></a>
<h3 class="register">Offset 0x0000: DIO_MASTER_REGISTER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('DIO_REGMAP|DIO_MASTER_REGISTER_in')">(<span id="show_DIO_REGMAP|DIO_MASTER_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIO_REGMAP|DIO_MASTER_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|DIO">CORE_REGS_REGMAP|DIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_MASTER_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A2000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL">RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL</a></td></tr>
<tr><td class="offset_info" align="right"> 0x001000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00D000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_dio.v.<BR/>
It uses RegType <b>DIO_CONTROL_REG</b> which is defined in HDL source file x4xx_dio.v.</p>
</div>
<div class="info">
Holds a single bit setting for DIO lines in both ports. One bit per pin.<BR/>
Sets whether the DIO signal line is driven by this register interface
or the user application.<br/>
0 = user application is master, 1 = output of <a href="#DIO_REGMAP|SW_DIO_CONTROL">SW_DIO_CONTROL</a> is master
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|DIO_MASTER_REGISTER|DIO_PORT_B"></a>DIO_PORT_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|DIO_MASTER_REGISTER|DIO_PORT_A"></a>DIO_PORT_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIO_REGMAP|DIO_DIRECTION_REGISTER"></a>
<h3 class="register">Offset 0x0004: DIO_DIRECTION_REGISTER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('DIO_REGMAP|DIO_DIRECTION_REGISTER_in')">(<span id="show_DIO_REGMAP|DIO_DIRECTION_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIO_REGMAP|DIO_DIRECTION_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|DIO">CORE_REGS_REGMAP|DIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_DIRECTION_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0004</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A2004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL">RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL</a></td></tr>
<tr><td class="offset_info" align="right"> 0x001000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00D004
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_dio.v.<BR/>
It uses RegType <b>DIO_CONTROL_REG</b> which is defined in HDL source file x4xx_dio.v.</p>
</div>
<div class="info">
Holds a single bit setting for DIO lines in both ports. One bit per pin.<BR/>
Set the direction of FPGA buffer connected to DIO ports on the DIO board.<br/>
Each bit represents one signal line. 0 = line is an input to the FPGA,
1 = line is an output driven by the FPGA.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|DIO_DIRECTION_REGISTER|DIO_PORT_B"></a>DIO_PORT_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|DIO_DIRECTION_REGISTER|DIO_PORT_A"></a>DIO_PORT_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIO_REGMAP|DIO_INPUT_REGISTER"></a>
<h3 class="register">Offset 0x0008: DIO_INPUT_REGISTER Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('DIO_REGMAP|DIO_INPUT_REGISTER_in')">(<span id="show_DIO_REGMAP|DIO_INPUT_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIO_REGMAP|DIO_INPUT_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|DIO">CORE_REGS_REGMAP|DIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_INPUT_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0008</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A2008
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL">RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL</a></td></tr>
<tr><td class="offset_info" align="right"> 0x001000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00D008
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_dio.v.<BR/>
It uses RegType <b>DIO_CONTROL_REG</b> which is defined in HDL source file x4xx_dio.v.</p>
</div>
<div class="info">
Holds a single bit setting for DIO lines in both ports. One bit per pin.<BR/>
Status of each bit at the FPGA input.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|DIO_INPUT_REGISTER|DIO_PORT_B"></a>DIO_PORT_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|DIO_INPUT_REGISTER|DIO_PORT_A"></a>DIO_PORT_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIO_REGMAP|DIO_OUTPUT_REGISTER"></a>
<h3 class="register">Offset 0x000C: DIO_OUTPUT_REGISTER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('DIO_REGMAP|DIO_OUTPUT_REGISTER_in')">(<span id="show_DIO_REGMAP|DIO_OUTPUT_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIO_REGMAP|DIO_OUTPUT_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|DIO">CORE_REGS_REGMAP|DIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_OUTPUT_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x000C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A200C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL">RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL</a></td></tr>
<tr><td class="offset_info" align="right"> 0x001000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00D00C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_dio.v.<BR/>
It uses RegType <b>DIO_CONTROL_REG</b> which is defined in HDL source file x4xx_dio.v.</p>
</div>
<div class="info">
Holds a single bit setting for DIO lines in both ports. One bit per pin.<BR/>
Controls the values on each DIO signal line in case the line master is
set to PS in <a href="#DIO_REGMAP|DIO_MASTER_REGISTER">DIO_MASTER_REGISTER</a>.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|DIO_OUTPUT_REGISTER|DIO_PORT_B"></a>DIO_PORT_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|DIO_OUTPUT_REGISTER|DIO_PORT_A"></a>DIO_PORT_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIO_REGMAP|DIO_SOURCE_REGISTER"></a>
<h3 class="register">Offset 0x0010: DIO_SOURCE_REGISTER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('DIO_REGMAP|DIO_SOURCE_REGISTER_in')">(<span id="show_DIO_REGMAP|DIO_SOURCE_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIO_REGMAP|DIO_SOURCE_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|DIO">CORE_REGS_REGMAP|DIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_SOURCE_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0010</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A2010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL">RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL</a></td></tr>
<tr><td class="offset_info" align="right"> 0x001000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00D010
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_dio.v.<BR/>
It uses RegType <b>DIO_CONTROL_REG</b> which is defined in HDL source file x4xx_dio.v.</p>
</div>
<div class="info">
Holds a single bit setting for DIO lines in both ports. One bit per pin.<BR/>
Controls whether the DIO lines reflect the state of <a href="#DIO_REGMAP|DIO_MASTER_REGISTER">DIO_MASTER_REGISTER</a>
or the radio blocks. 0 = <a href="#DIO_REGMAP|DIO_MASTER_REGISTER">DIO_MASTER_REGISTER</a>,
1 = Radio block output(<a href="#DIO_REGMAP|DIO_OVERRIDE">DIO_OVERRIDE</a>)
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|DIO_SOURCE_REGISTER|DIO_PORT_B"></a>DIO_PORT_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|DIO_SOURCE_REGISTER|DIO_PORT_A"></a>DIO_PORT_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIO_REGMAP|RADIO_SOURCE_REGISTER"></a>
<h3 class="register">Offset 0x0014: RADIO_SOURCE_REGISTER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('DIO_REGMAP|RADIO_SOURCE_REGISTER_in')">(<span id="show_DIO_REGMAP|RADIO_SOURCE_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIO_REGMAP|RADIO_SOURCE_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|DIO">CORE_REGS_REGMAP|DIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RADIO_SOURCE_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0014</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A2014
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL">RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL</a></td></tr>
<tr><td class="offset_info" align="right"> 0x001000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00D014
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_dio.v.<BR/>
It uses RegType <b>DIO_CONTROL_REG</b> which is defined in HDL source file x4xx_dio.v.</p>
</div>
<div class="info">
Holds a single bit setting for DIO lines in both ports. One bit per pin.<BR/>
Controls which radio block to use the ATR state from to determine the
state of the DIO lines.
0 = Radio#0
1 = Radio#1
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|RADIO_SOURCE_REGISTER|DIO_PORT_B"></a>DIO_PORT_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|RADIO_SOURCE_REGISTER|DIO_PORT_A"></a>DIO_PORT_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIO_REGMAP|INTERFACE_DIO_SELECT"></a>
<h3 class="register">Offset 0x0018: INTERFACE_DIO_SELECT Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('DIO_REGMAP|INTERFACE_DIO_SELECT_in')">(<span id="show_DIO_REGMAP|INTERFACE_DIO_SELECT_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIO_REGMAP|INTERFACE_DIO_SELECT_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|DIO">CORE_REGS_REGMAP|DIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">INTERFACE_DIO_SELECT</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0018</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A2018
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL">RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL</a></td></tr>
<tr><td class="offset_info" align="right"> 0x001000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00D018
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_dio.v.<BR/>
It uses RegType <b>DIO_CONTROL_REG</b> which is defined in HDL source file x4xx_dio.v.</p>
</div>
<div class="info">
Holds a single bit setting for DIO lines in both ports. One bit per pin.<BR/>
Controls which of the two available digital interfaces controls the DIO lines.
0 = Digital interface from Radio#0,
1 = Digital Interface from Radio#1.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|INTERFACE_DIO_SELECT|DIO_PORT_B"></a>DIO_PORT_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|INTERFACE_DIO_SELECT|DIO_PORT_A"></a>DIO_PORT_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIO_REGMAP|DIO_OVERRIDE"></a>
<h3 class="register">Offset 0x001C: DIO_OVERRIDE Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('DIO_REGMAP|DIO_OVERRIDE_in')">(<span id="show_DIO_REGMAP|DIO_OVERRIDE_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIO_REGMAP|DIO_OVERRIDE_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|DIO">CORE_REGS_REGMAP|DIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_OVERRIDE</td></tr>
<tr><td class="offset_info" align="right"> offset=0x001C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A201C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL">RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL</a></td></tr>
<tr><td class="offset_info" align="right"> 0x001000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00D01C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_dio.v.<BR/>
It uses RegType <b>DIO_CONTROL_REG</b> which is defined in HDL source file x4xx_dio.v.</p>
</div>
<div class="info">
Holds a single bit setting for DIO lines in both ports. One bit per pin.<BR/>
Controls whether the radio input to the <a href="#DIO_REGMAP|DIO_SOURCE_REGISTER">DIO_SOURCE_REGISTER</a> mux
connects to the ATR control or a Digital interface block. The output
of the mux controlled by this bit goes to <a href="#DIO_REGMAP|DIO_SOURCE_REGISTER">DIO_SOURCE_REGISTER</a>.
0 = Drive the ATR state(<a href="#DIO_REGMAP|RADIO_SOURCE_REGISTER">RADIO_SOURCE_REGISTER</a>), 1 = Drive
Digital interface block(Output of <a href="#DIO_REGMAP|INTERFACE_DIO_SELECT">INTERFACE_DIO_SELECT</a>).
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|DIO_OVERRIDE|DIO_PORT_B"></a>DIO_PORT_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|DIO_OVERRIDE|DIO_PORT_A"></a>DIO_PORT_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIO_REGMAP|SW_DIO_CONTROL"></a>
<h3 class="register">Offset 0x0020: SW_DIO_CONTROL Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('DIO_REGMAP|SW_DIO_CONTROL_in')">(<span id="show_DIO_REGMAP|SW_DIO_CONTROL_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIO_REGMAP|SW_DIO_CONTROL_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|DIO">CORE_REGS_REGMAP|DIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SW_DIO_CONTROL</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0020</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A2020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL">RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL</a></td></tr>
<tr><td class="offset_info" align="right"> 0x001000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00D020
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_dio.v.<BR/>
It uses RegType <b>DIO_CONTROL_REG</b> which is defined in HDL source file x4xx_dio.v.</p>
</div>
<div class="info">
Holds a single bit setting for DIO lines in both ports. One bit per pin.<BR/>
Controls which source is forwarded to the <a href="#DIO_REGMAP|DIO_MASTER_REGISTER">DIO_MASTER_REGISTER</a> mux.
This configuration is applied independently for each DIO line.
0 = MPM Ctrlport endpoint, 1 = PS Netlist DIO signal.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|SW_DIO_CONTROL|DIO_PORT_B"></a>DIO_PORT_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="DIO_REGMAP|SW_DIO_CONTROL|DIO_PORT_A"></a>DIO_PORT_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="regmap">
<a name="DMA_REGMAP"></a>
<h1 class="regmap">DMA_REGMAP</h1>
<div class="xmlpmd">
</div>
<div class="group"><a name="DMA_REGMAP|XILINX_DMA_REGISTERS"></a><h2 class="group">XILINX_DMA_REGISTERS</h2>
<div class="xmlpmd">
<p>Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11</p>
<ul>
<li>https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf</li>
</ul></div>
</div>
</div>
<div class="regmap">
<a name="ETH_DMA_CTRL_REGMAP"></a>
<h1 class="regmap">ETH_DMA_CTRL_REGMAP</h1>
This is the map that the nixge driver uses in Ethernet DMA to
move data between the Processing System's architecture and the fabric.
This map is a combination of two main components: a Xilix AXI DMA engine
and some registers for MAC/PHY control.
<div class="group"><a name="ETH_DMA_CTRL_REGMAP|ETH_DMA_CTRL"></a><h2 class="group">ETH_DMA_CTRL</h2>
<div class="register">
<a name="ETH_DMA_CTRL_REGMAP|AXI_DMA_CTRL"></a>
<h3 class="register">Offset 0x0000: AXI_DMA_CTRL Window (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('ETH_DMA_CTRL_REGMAP|AXI_DMA_CTRL_in')">(<span id="show_ETH_DMA_CTRL_REGMAP|AXI_DMA_CTRL_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_ETH_DMA_CTRL_REGMAP|AXI_DMA_CTRL_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|INT_ETH_DMA">AXI_HPM0_REGMAP|INT_ETH_DMA</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A4000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">AXI_DMA_CTRL</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
<tr><td class="offset_info" align="right"> size=0x4000 (16 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A4000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
Refer to Xilinx' AXI DMA v7.1 IP product guide for further
information on this register map:
https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
</div>
</div>
<div class="register">
<a name="ETH_DMA_CTRL_REGMAP|ETH_IO_CTRL"></a>
<h3 class="register">Offset 0x4000: ETH_IO_CTRL Window (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('ETH_DMA_CTRL_REGMAP|ETH_IO_CTRL_in')">(<span id="show_ETH_DMA_CTRL_REGMAP|ETH_IO_CTRL_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_ETH_DMA_CTRL_REGMAP|ETH_IO_CTRL_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|INT_ETH_DMA">AXI_HPM0_REGMAP|INT_ETH_DMA</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A4000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">ETH_IO_CTRL</td></tr>
<tr><td class="offset_info" align="right"> offset=0x4000</td></tr>
<tr><td class="offset_info" align="right"> size=0x2000 (8 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A8000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
MAC/PHY control for the Ethernet interface.
</div>
</div>
</div>
</div>
<div class="regmap">
<a name="GLOBAL_REGS_REGMAP"></a>
<h1 class="regmap">GLOBAL_REGS_REGMAP</h1>
<div class="group"><a name="GLOBAL_REGS_REGMAP|GLOBAL_REGS"></a><h2 class="group">GLOBAL_REGS</h2>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|COMPAT_NUM_REG"></a>
<h3 class="register">Offset 0x0000: COMPAT_NUM_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|COMPAT_NUM_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|COMPAT_NUM_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|COMPAT_NUM_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">COMPAT_NUM_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Revision number
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..16</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|COMPAT_NUM_REG|COMPAT_MAJOR"></a>COMPAT_MAJOR</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..0</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|COMPAT_NUM_REG|COMPAT_MINOR"></a>COMPAT_MINOR</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|DATESTAMP_REG"></a>
<h3 class="register">Offset 0x0004: DATESTAMP_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DATESTAMP_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DATESTAMP_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DATESTAMP_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DATESTAMP_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0004</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0004
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Build datestamp (32-bit)
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..27</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|DATESTAMP_REG|DAY"></a>DAY</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">26..23</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|DATESTAMP_REG|MONTH"></a>MONTH</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">22..17</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|DATESTAMP_REG|YEAR"></a>YEAR</span><span class="attr"> </span></p>
<p>This is the year number after 2000 (e.g. 2019 = d19).</p>
</td>
</tr>
<tr valign="top">
<td class="bits">16..12</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|DATESTAMP_REG|HOUR"></a>HOUR</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..6</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|DATESTAMP_REG|MINUTES"></a>MINUTES</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">5..0</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|DATESTAMP_REG|SECONDS"></a>SECONDS</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|GIT_HASH_REG"></a>
<h3 class="register">Offset 0x0008: GIT_HASH_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|GIT_HASH_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|GIT_HASH_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|GIT_HASH_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">GIT_HASH_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0008</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0008
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Git hash of source commit.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|SCRATCH_REG"></a>
<h3 class="register">Offset 0x000C: SCRATCH_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|SCRATCH_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|SCRATCH_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|SCRATCH_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SCRATCH_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x000C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A000C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Scratch register for testing.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|DEVICE_ID_REG"></a>
<h3 class="register">Offset 0x0010: DEVICE_ID_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DEVICE_ID_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DEVICE_ID_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DEVICE_ID_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DEVICE_ID_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0010</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0010
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Register that contains the motherboard's device ID.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|DEVICE_ID_REG|PCIE_PRESENT_BIT"></a>PCIE_PRESENT_BIT</span><span class="attr"> </span></p>
<p>Set to 1 if PCI-Express core is present in FPGA design.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">30..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..0</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|DEVICE_ID_REG|DEVICE_ID"></a>DEVICE_ID</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|RFNOC_INFO_REG"></a>
<h3 class="register">Offset 0x0014: RFNOC_INFO_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|RFNOC_INFO_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|RFNOC_INFO_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|RFNOC_INFO_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RFNOC_INFO_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0014</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0014
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Register that provides information on the RFNoC protocol.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..16</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|RFNOC_INFO_REG|CHDR_WIDTH"></a>CHDR_WIDTH</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|RFNOC_INFO_REG|RFNOC_PROTO_MAJOR"></a>RFNOC_PROTO_MAJOR</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..0</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|RFNOC_INFO_REG|RFNOC_PROTO_MINOR"></a>RFNOC_PROTO_MINOR</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG"></a>
<h3 class="register">Offset 0x0018: CLOCK_CTRL_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CLOCK_CTRL_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0018</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0018
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Control register for clocking resources.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY"></a>PPS_BRC_DELAY</span><span class="attr"> </span></p>
<p>Number of base reference clock cycles from appearance of the PPS
rising edge to the occurrence of the aligned edge of base reference
clock and PLL reference clock at the sample PLL output. This number
is the sum of the actual value based on <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PLL_SYNC_DELAY">PLL_SYNC_DELAY</a> (also
accumulate the fixed amount of clock cycles) and if any the number of
cycles the SPLL requires from issuing of the SYNC signal to the
aligned edge (with LMK04832 = 0).<br>
The number written to this register has to be reduced by 1 due to
HDL implementation.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PLL_SYNC_DELAY"></a>PLL_SYNC_DELAY</span><span class="attr"> </span></p>
<p>Due to the HDL implementation the rising edge of the SYNC signal for
the LMK04832 is generated 2 clock cycles after the PPS rising edge.
This delay can be further increased by setting this delay value
(e.g. PLL_SYNC_DELAY=3 will result in a total delay of 5 clock cycles).<br>
In case two X400 devices are connected using the PPS and reference clock the master delay value needs to be 3 clock cycles
higher than the slave delay value to align the LMK sync edges in time.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..10</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">9r</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PLL_SYNC_DONE"></a>PLL_SYNC_DONE</span><span class="attr"> </span></p>
<p>Indicates the success of the PLL reset started by <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PLL_SYNC_TRIGGER">PLL_SYNC_TRIGGER</a>. Reset on deassertion of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PLL_SYNC_TRIGGER">PLL_SYNC_TRIGGER</a>.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">8w</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PLL_SYNC_TRIGGER"></a>PLL_SYNC_TRIGGER</span><span class="attr"> </span></p>
<p>Assertion triggers the SYNC signal generation for LMK04832 after the next appearance of the PPS rising edge.
There is no self reset on this trigger.
Keep this trigger asserted until <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PLL_SYNC_DONE">PLL_SYNC_DONE</a> is asserted.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..6</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">5..4</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|TRIGGER_IO_SELECT"></a>TRIGGER_IO_SELECT</span><span class="attr"> (initialvalue=TRIG_IO_INPUT)</span></p>
<p><b>IMPORTANT!</b> SW must ensure any TRIG_IO consumers (downstream devices) <b>ignore
and/or re-sync after enabling this port</b>, since the output-enable is basically
asynchronous to the actual TRIG_IO driver.</p>
<p>
The values for this bitfield are in the TRIG_IO_ENUM table.
<a class="sh_enum" href="javascript:sb('GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|TRIGGER_IO_SELECT')">(<span id="show_GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|TRIGGER_IO_SELECT">show here</span>)</a>
</p>
<div class="sh_enum" id="div_GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|TRIGGER_IO_SELECT">
<div class="enum">
<a name="GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|TRIGGER_IO_SELECT|TRIG_IO_ENUM"></a>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' > Value </td>
<td class="l" colspan='1'> Name </td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|TRIGGER_IO_SELECT|TRIG_IO_ENUM|TRIG_IO_INPUT'></a>TRIG_IO_INPUT</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|TRIGGER_IO_SELECT|TRIG_IO_ENUM|TRIG_IO_PPS_OUTPUT'></a>TRIG_IO_PPS_OUTPUT</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file x4xx_global_regs.v.
</p>
</div>
</div>
</td>
</tr>
<tr valign="top">
<td class="bits">3r</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|REFCLK_LOCKED"></a>REFCLK_LOCKED</span><span class="attr"> </span></p>
<p>RESERVED. This bit is not implemented on X4xx and reads as 0.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">2</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|REF_SELECT"></a>REF_SELECT</span><span class="attr"> </span></p>
<p>RESERVED. This bit is not implemented on X4xx and reads as 0.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">1..0</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_SELECT"></a>PPS_SELECT</span><span class="attr"> (initialvalue=PPS_INT_25MHZ)</span></p>
<p>Select the source of the PPS signal.
For the internal generation the value depending on the base reference clock has to be chosen.
The external reference is taken from the PPS_IN pin and is independent of the base reference clock.</p>
<p>
The values for this bitfield are in the PPS_ENUM table.
<a class="sh_enum" href="javascript:sb('GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_SELECT')">(<span id="show_GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_SELECT">show here</span>)</a>
</p>
<div class="sh_enum" id="div_GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_SELECT">
<div class="enum">
<a name="GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_SELECT|PPS_ENUM"></a>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' > Value </td>
<td class="l" colspan='1'> Name </td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_SELECT|PPS_ENUM|PPS_INT_25MHZ'></a>PPS_INT_25MHZ</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_SELECT|PPS_ENUM|PPS_INT_10MHZ'></a>PPS_INT_10MHZ</p>
</td>
</tr>
<tr valign="top">
<td class='value'>2</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_SELECT|PPS_ENUM|PPS_EXT'></a>PPS_EXT</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file x4xx_global_regs.v.
</p>
</div>
</div>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG"></a>
<h3 class="register">Offset 0x001C: PPS_CTRL_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|PPS_CTRL_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|PPS_CTRL_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|PPS_CTRL_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">PPS_CTRL_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x001C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A001C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Control registers for PPS generation.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_RC_ENABLED"></a>PPS_RC_ENABLED</span><span class="attr"> </span></p>
<p>Enables the PPS signal in radio clock domain. Please make sure that
the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a> and <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC_DIVIDER">PRC_RC_DIVIDER</a> are
set before enabling this bit. It is recommended to disable the PPS
for changes on the other values. Use a wait time of at least 1 second
before changing this value to ensure the values are stable for the
next PPS edge.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">30</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">29..28</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC_DIVIDER"></a>PRC_RC_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock from PLL reference clock.
The value written to the register has to be reduced by 2 due to
HDL implementation.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..26</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">25..0</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY"></a>PPS_PRC_DELAY</span><span class="attr"> </span></p>
<p>The number of PLL reference clock cycles from one aligned edge to the
desired aligned edge to issue the PPS in radio clock domain. This
delay is configurable to any aligned edge within a maximum delay of 1
second (period of PPS). <br>
The value written to the register has to be reduced by 4 due to
HDL implementation.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG"></a>
<h3 class="register">Offset 0x0020: CHDR_CLK_RATE_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CHDR_CLK_RATE_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0020</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0020
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x0BEBC200
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Returns the RFNoC bus clock rate (CHDR).
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..0</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG|CHDR_CLK"></a>CHDR_CLK</span><span class="attr"> (initialvalue=CHDR_CLK_VALUE)</span></p>
<p></p>
<p>
The values for this bitfield are in the CHDR_CLK_ENUM table.
<a class="sh_enum" href="javascript:sb('GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG|CHDR_CLK')">(<span id="show_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG|CHDR_CLK">show here</span>)</a>
</p>
<div class="sh_enum" id="div_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG|CHDR_CLK">
<div class="enum">
<a name="GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG|CHDR_CLK|CHDR_CLK_ENUM"></a>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' colspan='2'> Value </td>
<td class="l" rowspan='2' colspan='1'> Name </td>
</tr>
<tr class="header2" valign="bottom">
<td class='value'> Dec </td>
<td class='l'> Hex </td>
</tr>
<tr valign="top">
<td class='value'>200000000</td>
<td class='l'>0xBEBC200</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG|CHDR_CLK|CHDR_CLK_ENUM|CHDR_CLK_VALUE'></a>CHDR_CLK_VALUE</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file x4xx_global_regs.v.
</p>
</div>
</div>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG"></a>
<h3 class="register">Offset 0x0024: CHDR_CLK_COUNT_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CHDR_CLK_COUNT_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0024</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0024
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Returns the count value of a free-running counter driven by the RFNoC
CHDR bus clock.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|GPS_CTRL_REG"></a>
<h3 class="register">Offset 0x0038: GPS_CTRL_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|GPS_CTRL_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|GPS_CTRL_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|GPS_CTRL_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">GPS_CTRL_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0038</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0038
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
RESERVED. This register is not implemented on X4xx. GPS is connected
to the PS via a UART.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|GPS_STATUS_REG"></a>
<h3 class="register">Offset 0x003C: GPS_STATUS_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|GPS_STATUS_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|GPS_STATUS_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|GPS_STATUS_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">GPS_STATUS_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x003C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A003C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
RESERVED. This register is not implemented on X4xx. GPS is connected
to the PS via a UART.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG"></a>
<h3 class="register">Offset 0x0040: DBOARD_CTRL_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DBOARD_CTRL_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0040</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0040
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
RESERVED. This register is not implemented on X4xx.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|DBOARD_STATUS_REG"></a>
<h3 class="register">Offset 0x0044: DBOARD_STATUS_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DBOARD_STATUS_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DBOARD_STATUS_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DBOARD_STATUS_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DBOARD_STATUS_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0044</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0044
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
RESERVED. This register is not implemented on X4xx.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|NUM_TIMEKEEPERS_REG"></a>
<h3 class="register">Offset 0x0048: NUM_TIMEKEEPERS_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|NUM_TIMEKEEPERS_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|NUM_TIMEKEEPERS_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|NUM_TIMEKEEPERS_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">NUM_TIMEKEEPERS_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0048</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0048
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Register that specifies the number of timekeepers in the core.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|SERIAL_NUM_LOW_REG"></a>
<h3 class="register">Offset 0x004C: SERIAL_NUM_LOW_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|SERIAL_NUM_LOW_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|SERIAL_NUM_LOW_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|SERIAL_NUM_LOW_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SERIAL_NUM_LOW_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x004C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A004C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Least significant bytes of 8 byte serial number
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|SERIAL_NUM_HIGH_REG"></a>
<h3 class="register">Offset 0x0050: SERIAL_NUM_HIGH_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|SERIAL_NUM_HIGH_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|SERIAL_NUM_HIGH_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|SERIAL_NUM_HIGH_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SERIAL_NUM_HIGH_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0050</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0050
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Most significant bytes of 8 byte serial number
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|MFG_TEST_CTRL_REG"></a>
<h3 class="register">Offset 0x0054: MFG_TEST_CTRL_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|MFG_TEST_CTRL_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|MFG_TEST_CTRL_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|MFG_TEST_CTRL_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">MFG_TEST_CTRL_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0054</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0054
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Control register for mfg_test functions.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..2</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">1</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|MFG_TEST_CTRL_REG|MFG_TEST_EN_FABRIC_CLK"></a>MFG_TEST_EN_FABRIC_CLK</span><span class="attr"> </span></p>
<p>When enabled, routes data_clk to FPGA_REF_CLK output port.
When disabled, the FPGA_REF_CLK output is driven to 0.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|MFG_TEST_CTRL_REG|MFG_TEST_EN_GTY_RCV_CLK"></a>MFG_TEST_EN_GTY_RCV_CLK</span><span class="attr"> </span></p>
<p>When enabled, routes data_clk to GTY_RCV_CLK output port.
When disabled, the GTY_RCV_CLK output is driven to 0.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|MFG_TEST_STATUS_REG"></a>
<h3 class="register">Offset 0x0058: MFG_TEST_STATUS_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|MFG_TEST_STATUS_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|MFG_TEST_STATUS_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|MFG_TEST_STATUS_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">MFG_TEST_STATUS_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0058</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0058
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Status register for mfg_test functions.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..26</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">25..0</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|MFG_TEST_STATUS_REG|MFG_TEST_FPGA_AUX_REF_FREQ"></a>MFG_TEST_FPGA_AUX_REF_FREQ</span><span class="attr"> </span></p>
<p>Report the time between rising edges on the FPGA_REF_CLK
input port in 40 MHz Clock ticks. If the count extends
to 1.2 seconds without an edge, the value reported is set
to zero.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|QSFP_PORT_0_0_INFO_REG"></a>
<h3 class="register">Offset 0x0060: QSFP_PORT_0_0_INFO_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|QSFP_PORT_0_0_INFO_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|QSFP_PORT_0_0_INFO_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|QSFP_PORT_0_0_INFO_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_PORT_0_0_INFO_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0060</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0060
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Returns information from the QSFP0 Lane0.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|QSFP_PORT_0_1_INFO_REG"></a>
<h3 class="register">Offset 0x0064: QSFP_PORT_0_1_INFO_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|QSFP_PORT_0_1_INFO_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|QSFP_PORT_0_1_INFO_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|QSFP_PORT_0_1_INFO_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_PORT_0_1_INFO_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0064</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0064
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Returns information from the QSFP0 Lane1.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|QSFP_PORT_0_2_INFO_REG"></a>
<h3 class="register">Offset 0x0068: QSFP_PORT_0_2_INFO_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|QSFP_PORT_0_2_INFO_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|QSFP_PORT_0_2_INFO_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|QSFP_PORT_0_2_INFO_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_PORT_0_2_INFO_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0068</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0068
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Returns information from the QSFP0 Lane2.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|QSFP_PORT_0_3_INFO_REG"></a>
<h3 class="register">Offset 0x006C: QSFP_PORT_0_3_INFO_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|QSFP_PORT_0_3_INFO_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|QSFP_PORT_0_3_INFO_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|QSFP_PORT_0_3_INFO_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_PORT_0_3_INFO_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x006C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A006C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Returns information from the QSFP0 Lane3.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG"></a>
<h3 class="register">Offset 0x0070: QSFP_PORT_1_0_INFO_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_PORT_1_0_INFO_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0070</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0070
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Returns information from the QSFP1 Lane0.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG"></a>
<h3 class="register">Offset 0x0074: QSFP_PORT_1_1_INFO_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_PORT_1_1_INFO_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0074</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0074
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Returns information from the QSFP1 Lane1.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG"></a>
<h3 class="register">Offset 0x0078: QSFP_PORT_1_2_INFO_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_PORT_1_2_INFO_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0078</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0078
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Returns information from the QSFP1 Lane2.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG"></a>
<h3 class="register">Offset 0x007C: QSFP_PORT_1_3_INFO_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">QSFP_PORT_1_3_INFO_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x007C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A007C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Returns information from the QSFP1 Lane3.
</div>
</div>
</div>
</div>
<div class="regmap">
<a name="GPIO_ATR_REGMAP"></a>
<h1 class="regmap">GPIO_ATR_REGMAP</h1>
<div class="group"><a name="GPIO_ATR_REGMAP|GPIO_ATR_REGS"></a><h2 class="group">GPIO_ATR_REGS</h2>
Describes the behavior of GPIO lines when controlled by the ATR state.
<div class="register">
<a name="GPIO_ATR_REGMAP|ATR_STATE"></a>
<h3 class="register">Offset 0x0000: ATR_STATE(15:0) Register Array (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GPIO_ATR_REGMAP|ATR_STATE_in')">(<span id="show_GPIO_ATR_REGMAP|ATR_STATE_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GPIO_ATR_REGMAP|ATR_STATE_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS">RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">ATR_STATE</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000 + i*4</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00C000 + i*4
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info"><B>Initial Values</B><BR/>
<table>
<tr><td>default</td><td>=></td><td>0x00000000</td></tr>
</table>
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_atr.v.<BR/>
It uses RegType <b>GPIO_ATR_STATE</b> which is defined in HDL source file x4xx_gpio_atr.v.</p>
</div>
<div class="info">
Holds a single bit setting for GPIO lines in both ports for a particular ATR sate<BR/>
Describes GPIO behavior for the different ATR states. When <a href="#GPIO_ATR_REGMAP|ATR_OPTION_REGISTRER|ATR_OPTION">ATR_OPTION</a>
is set to use the DB states, TX and RX states for RF0 and RF1 are
combined to create a single vector. This creates 16 different
combinations, each with its own register. When <a href="#GPIO_ATR_REGMAP|ATR_OPTION_REGISTRER|ATR_OPTION">ATR_OPTION</a> is set to
classic ATR, offsets 0x00-0x03 in this register group will be driven
in accordance with the state of RF0, and offsets 0x04-0x07 will be
driven in accordance with the state of RF1.
CLASSIC ATR MAPPING: Idle[RF0:0x00; RF1:0x04], RX[RF0:0x01; RF1:0x05],
TX[RF0:0x02; RF1:0x06], FDX[RF0:0x03; RF1:0x07]
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="GPIO_ATR_REGMAP|ATR_STATE|GPIO_STATE_B"></a>GPIO_STATE_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="GPIO_ATR_REGMAP|ATR_STATE|GPIO_STATE_A"></a>GPIO_STATE_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GPIO_ATR_REGMAP|CLASSIC_ATR_CONFIG"></a>
<h3 class="register">Offset 0x0040: CLASSIC_ATR_CONFIG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GPIO_ATR_REGMAP|CLASSIC_ATR_CONFIG_in')">(<span id="show_GPIO_ATR_REGMAP|CLASSIC_ATR_CONFIG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GPIO_ATR_REGMAP|CLASSIC_ATR_CONFIG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS">RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CLASSIC_ATR_CONFIG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0040</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00C040
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_atr.v.</p>
</div>
<div class="info">
Controls the RF state mapping of each GPIO line when classic
ATR mode is active.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="GPIO_ATR_REGMAP|CLASSIC_ATR_CONFIG|RF_SELECT_B"></a>RF_SELECT_B</span><span class="attr"> (initialvalue=0)</span></p>
<p>Set which RF channel's state to reflect in the pins of
HDMI connector B when <a href="#GPIO_ATR_REGMAP|ATR_OPTION_REGISTRER|ATR_OPTION">ATR_OPTION</a> is set to classic ATR.
Controlled in a per-pin basis.
0 = RF0 State(GPIO_ATR_STATE 0x00-0x03)
1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="GPIO_ATR_REGMAP|CLASSIC_ATR_CONFIG|RF_SELECT_A"></a>RF_SELECT_A</span><span class="attr"> (initialvalue=0)</span></p>
<p>Set which RF channel's state to reflect in the pins for
HDMI connector A when <a href="#GPIO_ATR_REGMAP|ATR_OPTION_REGISTRER|ATR_OPTION">ATR_OPTION</a> is set to classic ATR.
Controlled in a per-pin basis.
0 = RF0 State(GPIO_ATR_STATE 0x00-0x03)
1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GPIO_ATR_REGMAP|ATR_OPTION_REGISTRER"></a>
<h3 class="register">Offset 0x0044: ATR_OPTION_REGISTRER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GPIO_ATR_REGMAP|ATR_OPTION_REGISTRER_in')">(<span id="show_GPIO_ATR_REGMAP|ATR_OPTION_REGISTRER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GPIO_ATR_REGMAP|ATR_OPTION_REGISTRER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS">RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">ATR_OPTION_REGISTRER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0044</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00C044
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_atr.v.</p>
</div>
<div class="info">
Controls whether GPIO lines use the TX and RX state of an RF channel
(Classic ATR) or the daughterboard state the selector for the
<a href="#GPIO_ATR_REGMAP|ATR_STATE">ATR_STATE</a>.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..1</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="GPIO_ATR_REGMAP|ATR_OPTION_REGISTRER|ATR_OPTION"></a>ATR_OPTION</span><span class="attr"> (initialvalue=0)</span></p>
<p>Sets the scheme in which RF states in the radio will control GPIO
lines. 0 = DB state is used. RF states are combined and the
GPIO state is driven based on all 16 <a href="#GPIO_ATR_REGMAP|ATR_STATE">ATR_STATE</a> registers.
1 = Each RF channel has its separate ATR state(Classic ATR).
Use register <a href="#GPIO_ATR_REGMAP|CLASSIC_ATR_CONFIG">CLASSIC_ATR_CONFIG</a> to indicate the RF channel
to which each GPIO line responds to.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GPIO_ATR_REGMAP|GPIO_DIR"></a>
<h3 class="register">Offset 0x0048: GPIO_DIR Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GPIO_ATR_REGMAP|GPIO_DIR_in')">(<span id="show_GPIO_ATR_REGMAP|GPIO_DIR_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GPIO_ATR_REGMAP|GPIO_DIR_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS">RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">GPIO_DIR</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0048</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00C048
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_atr.v.</p>
</div>
<div class="info">
Controls the direction of each GPIO signal when controlled by the radio state.
0 = GPIO pin set to input. 1 = GPIO pin set to output
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="GPIO_ATR_REGMAP|GPIO_DIR|GPIO_DIR_B"></a>GPIO_DIR_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="GPIO_ATR_REGMAP|GPIO_DIR|GPIO_DIR_A"></a>GPIO_DIR_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GPIO_ATR_REGMAP|GPIO_DISABLED"></a>
<h3 class="register">Offset 0x004C: GPIO_DISABLED Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GPIO_ATR_REGMAP|GPIO_DISABLED_in')">(<span id="show_GPIO_ATR_REGMAP|GPIO_DISABLED_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GPIO_ATR_REGMAP|GPIO_DISABLED_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS">RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">GPIO_DISABLED</td></tr>
<tr><td class="offset_info" align="right"> offset=0x004C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00C04C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_atr.v.</p>
</div>
<div class="info">
Disable ATR Control. DB state 0 will be reflected regardless of the ATR state.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="GPIO_ATR_REGMAP|GPIO_DISABLED|GPIO_DISABLED_B"></a>GPIO_DISABLED_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="GPIO_ATR_REGMAP|GPIO_DISABLED|GPIO_DISABLED_A"></a>GPIO_DISABLED_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="GPIO_ATR_REGMAP|GPIO_IN"></a>
<h3 class="register">Offset 0x0050: GPIO_IN Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GPIO_ATR_REGMAP|GPIO_IN_in')">(<span id="show_GPIO_ATR_REGMAP|GPIO_IN_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GPIO_ATR_REGMAP|GPIO_IN_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS">RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">GPIO_IN</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0050</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00C050
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_atr.v.</p>
</div>
<div class="info">
Reflects the logic state of each GPIO input.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="GPIO_ATR_REGMAP|GPIO_IN|GPIO_IN_B"></a>GPIO_IN_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="GPIO_ATR_REGMAP|GPIO_IN|GPIO_IN_A"></a>GPIO_IN_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="regmap">
<a name="JTAG_REGMAP"></a>
<h1 class="regmap">JTAG_REGMAP</h1>
<div class="xmlpmd">
</div>
<div class="group"><a name="JTAG_REGMAP|JTAG_REGS"></a><h2 class="group">JTAG_REGS</h2>
<div class="xmlpmd">
<p>This register map is present for each JTAG module.</p>
<p>Basic operation would be:</p>
<ul>
<li>poll <a href="#JTAG_REGMAP|CONTROL|ready">ready</a> until asserted</li>
<li>write / read data</li>
<li>write <a href="#JTAG_REGMAP|CONTROL">CONTROL</a> register along with <a href="#JTAG_REGMAP|CONTROL|reset">reset</a> deasserted to start a transaction</li>
</ul>
<p>For resetting the BITQ FSM, simply assert <a href="#JTAG_REGMAP|CONTROL|reset">reset</a>.</p>
<p>This operation seems a little strange, but it is what the axi_bitq driver
expects. This behavior has been implemented in previous products.</p></div>
<div class="register">
<a name="JTAG_REGMAP|TX_DATA"></a>
<h3 class="register">Offset 0x0000: TX_DATA Register (W)</h3>
<a class="sh_addrs" href="javascript:sa('JTAG_REGMAP|TX_DATA_in')">(<span id="show_JTAG_REGMAP|TX_DATA_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_JTAG_REGMAP|TX_DATA_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|JTAG_DB0">MB_CPLD_PL_REGMAP|JTAG_DB0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000060</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">TX_DATA</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088060
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|JTAG_DB1">MB_CPLD_PL_REGMAP|JTAG_DB1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000080</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088080
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ctrlport_to_jtag.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Data to be transmitted (TDI)</p></div>
</div>
</div>
<div class="register">
<a name="JTAG_REGMAP|STB_DATA"></a>
<h3 class="register">Offset 0x0004: STB_DATA Register (W)</h3>
<a class="sh_addrs" href="javascript:sa('JTAG_REGMAP|STB_DATA_in')">(<span id="show_JTAG_REGMAP|STB_DATA_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_JTAG_REGMAP|STB_DATA_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|JTAG_DB0">MB_CPLD_PL_REGMAP|JTAG_DB0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000060</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">STB_DATA</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0004</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088064
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|JTAG_DB1">MB_CPLD_PL_REGMAP|JTAG_DB1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000080</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088084
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ctrlport_to_jtag.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Data to be transmitted (TMS)</p></div>
</div>
</div>
<div class="register">
<a name="JTAG_REGMAP|CONTROL"></a>
<h3 class="register">Offset 0x0008: CONTROL Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('JTAG_REGMAP|CONTROL_in')">(<span id="show_JTAG_REGMAP|CONTROL_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_JTAG_REGMAP|CONTROL_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|JTAG_DB0">MB_CPLD_PL_REGMAP|JTAG_DB0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000060</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CONTROL</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0008</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088068
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|JTAG_DB1">MB_CPLD_PL_REGMAP|JTAG_DB1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000080</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088088
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000001
</p>
<p class="reg_info">This register is defined in HDL source file ctrlport_to_jtag.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>JTAG module status and control</p></div>
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31r</td>
<td>
<p><span class="name"><a name="JTAG_REGMAP|CONTROL|ready"></a>ready</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>Bitq FSM is ready for input (no data transmission in progress).</p></div></p>
</td>
</tr>
<tr valign="top">
<td class="bits">31w</td>
<td>
<p><span class="name"><a name="JTAG_REGMAP|CONTROL|reset"></a>reset</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>When asserted ('1') a soft-reset for the bitq FSM is triggered,
preventing any transactions to take place.</p>
<p>Deassert this bit, along with values for <a href="#JTAG_REGMAP|CONTROL|prescalar">prescalar</a> and <a href="#JTAG_REGMAP|CONTROL|length">length</a>
to trigger a new transaction (start strobe).</p></div></p>
</td>
</tr>
<tr valign="top">
<td class="bits">30..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..13</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">12..8</td>
<td>
<p><span class="name"><a name="JTAG_REGMAP|CONTROL|length"></a>length</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>(Number of bits - 1) to be transferred</p></div></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..0</td>
<td>
<p><span class="name"><a name="JTAG_REGMAP|CONTROL|prescalar"></a>prescalar</span><span class="attr"> (initialvalue=true)</span></p>
<p><div class="xmlpmd">
<p>Clock divider. Resulting JTAG frequency will be f_ctrlport / (2*(prescalar + 1)). See window description for details on the initial/minimum value.</p></div></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="JTAG_REGMAP|RX_DATA"></a>
<h3 class="register">Offset 0x000C: RX_DATA Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('JTAG_REGMAP|RX_DATA_in')">(<span id="show_JTAG_REGMAP|RX_DATA_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_JTAG_REGMAP|RX_DATA_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|JTAG_DB0">MB_CPLD_PL_REGMAP|JTAG_DB0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000060</td></tr>
</table>
</td>
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RX_DATA</td></tr>
<tr><td class="offset_info" align="right"> offset=0x000C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x100008806C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|JTAG_DB1">MB_CPLD_PL_REGMAP|JTAG_DB1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000080</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x100008808C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ctrlport_to_jtag.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Received data (TDO)</p></div>
</div>
</div>
</div>
</div>
<div class="regmap">
<a name="MB_CPLD_PL_REGMAP"></a>
<h1 class="regmap">MB_CPLD_PL_REGMAP</h1>
<div class="xmlpmd">
<p>This register map is available using the PL CPLD SPI interface.
All protocol masters controller by this register map are running with a clock frequency of 50 MHz.</p></div>
<div class="group"><a name="MB_CPLD_PL_REGMAP|MB_CPLD_PL_WINDOWS"></a><h2 class="group">MB_CPLD_PL_WINDOWS</h2>
<div class="xmlpmd">
</div>
<div class="register">
<a name="MB_CPLD_PL_REGMAP|PL_REGISTERS"></a>
<h3 class="register">Offset 0x0000: PL_REGISTERS Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#PL_CPLD_BASE_REGMAP">PL_CPLD_BASE_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('MB_CPLD_PL_REGMAP|PL_REGISTERS_in')">(<span id="show_MB_CPLD_PL_REGMAP|PL_REGISTERS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_MB_CPLD_PL_REGMAP|PL_REGISTERS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">PL_REGISTERS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
<tr><td class="offset_info" align="right"> size=0x40 (64 bytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file mb_cpld.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
<div class="register">
<a name="MB_CPLD_PL_REGMAP|JTAG_DB0"></a>
<h3 class="register">Offset 0x0060: JTAG_DB0 Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#JTAG_REGMAP">JTAG_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('MB_CPLD_PL_REGMAP|JTAG_DB0_in')">(<span id="show_MB_CPLD_PL_REGMAP|JTAG_DB0_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_MB_CPLD_PL_REGMAP|JTAG_DB0_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">JTAG_DB0</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0060</td></tr>
<tr><td class="offset_info" align="right"> size=0x20 (32 bytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088060
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file mb_cpld.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>JTAG Master connected to first daugherboard's CPLD JTAG interface.</p>
<p><strong>Use minimum value of 1 for <a href="#JTAG_REGMAP|CONTROL|prescalar">JTAG_REGMAP.prescalar</a> because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.</strong></p></div>
</div>
</div>
<div class="register">
<a name="MB_CPLD_PL_REGMAP|JTAG_DB1"></a>
<h3 class="register">Offset 0x0080: JTAG_DB1 Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#JTAG_REGMAP">JTAG_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('MB_CPLD_PL_REGMAP|JTAG_DB1_in')">(<span id="show_MB_CPLD_PL_REGMAP|JTAG_DB1_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_MB_CPLD_PL_REGMAP|JTAG_DB1_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">JTAG_DB1</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0080</td></tr>
<tr><td class="offset_info" align="right"> size=0x20 (32 bytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088080
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file mb_cpld.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>JTAG Master connected to second daugherboard's CPLD JTAG interface.</p>
<p><strong>Use minimum value of 1 for <a href="#JTAG_REGMAP|CONTROL|prescalar">JTAG_REGMAP.prescalar</a> because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.</strong></p></div>
</div>
</div>
</div>
</div>
<div class="regmap">
<a name="NIXGE_REGMAP"></a>
<h1 class="regmap">NIXGE_REGMAP</h1>
<div class="xmlpmd">
</div>
<div class="group"><a name="NIXGE_REGMAP|XGE_MAC_REGS"></a><h2 class="group">XGE_MAC_REGS</h2>
<div class="xmlpmd">
<p>nixge (maps to 10g mac if present)</p></div>
<div class="register">
<a name="NIXGE_REGMAP|PORT_INFO"></a>
<h3 class="register">Offset 0x0000: PORT_INFO Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('NIXGE_REGMAP|PORT_INFO_in')">(<span id="show_NIXGE_REGMAP|PORT_INFO_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_NIXGE_REGMAP|PORT_INFO_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|NIXGE">QSFP_REGMAP|NIXGE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">PORT_INFO</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200008000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200018000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200028000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200038000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200048000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200058000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200068000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200078000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name"><a name="NIXGE_REGMAP|PORT_INFO|COMPAT_NUM"></a>COMPAT_NUM</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>Constant indicating version for this space.
Not used by the NIXGE driver (12/4/2020)</p></div></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..18</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">17</td>
<td>
<p><span class="name"><a name="NIXGE_REGMAP|PORT_INFO|ACTIVITY"></a>ACTIVITY</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>Generically this mirrors the activity LED. Specific meaning varies based on the MGT_PROTOCOL.</p></div></p>
</td>
</tr>
<tr valign="top">
<td class="bits">16</td>
<td>
<p><span class="name"><a name="NIXGE_REGMAP|PORT_INFO|LINK_UP"></a>LINK_UP</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>Generically means that a connection with a peer has been established. Specific
meaning varies based on the MGT_PROTOCOL.</p></div></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name"><a name="NIXGE_REGMAP|PORT_INFO|MGT_PROTOCOL"></a>MGT_PROTOCOL</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>Constant indicating what flavor of communication this port is using</p>
<ul>
<li>0 = NONE</li>
<li>1 = 1GbE</li>
<li>2 = 10GbE</li>
<li>3 = Aurora</li>
<li>4 = WhiteRabbit</li>
<li>5 = 100GbE</li>
</ul></div></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..0</td>
<td>
<p><span class="name"><a name="NIXGE_REGMAP|PORT_INFO|PORTNUM"></a>PORTNUM</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>Constant indicating which port this register is hooked to</p>
<ul>
<li>0 = QSFP0</li>
<li>1 = QSFP1</li>
</ul></div></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="NIXGE_REGMAP|MAC_CTRL_STATUS"></a>
<h3 class="register">Offset 0x0004: MAC_CTRL_STATUS Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('NIXGE_REGMAP|MAC_CTRL_STATUS_in')">(<span id="show_NIXGE_REGMAP|MAC_CTRL_STATUS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_NIXGE_REGMAP|MAC_CTRL_STATUS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|NIXGE">QSFP_REGMAP|NIXGE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">MAC_CTRL_STATUS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0004</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200008004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200018004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200028004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200038004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200048004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200058004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200068004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200078004
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Definition of this register depends on Protocol</p>
<p><strong>10GBE</strong></p>
<p><em>READ - Status</em></p>
<ul>
<li>0 = status_crc_error</li>
<li>1 = status_fragment_error</li>
<li>2 = status_txdfifo_ovflow</li>
<li>3 = status_txdfifo_udflow</li>
<li>4 = status_rxdfifo_ovflow</li>
<li>5 = status_rxdfifo_udflow</li>
<li>6 = status_pause_frame_rx</li>
<li>7 = status_local_fault</li>
<li>8 = status_remote_fault</li>
</ul>
<p><em>WRITE - Ctl</em></p>
<ul>
<li>0 = ctrl_tx_enable</li>
</ul>
<p><strong>100 GBE</strong></p>
<p><em>READ - Status</em></p>
<ul>
<li>0 = tx_ovfout - Sets if TX overflow reported by CMAC
(Stays set till MAC is reset). This is a fatal error</li>
<li>1 = tx_unfout - Sets if TX underflow reported by CMAC
(Stays set till MAC is reset). This is a fatal error</li>
<li>2 = stat_rx_aligned - goes high when CMAC has finished
alignment, and is ready to start reception of traffic.</li>
<li>3 = mac_dropped_packet - If the mac RX wants to push data(TVALID)
but upstream is trying to hold(TREADY)off we drop a packet.
Upstream circuitry should detect this when traffic is forked
between CHDR and CPU, so this bit will only set if there is a
HW design error.</li>
<li>4 = auto_config_done - This bit goes high when the auto_config
state machine finishes operation. It is very similiar to
stat_rx_alligned, but waits for extra writes which occur
after allignement to complete.</li>
<li>24:16 = pause_mask - readable version of pause_mask bellow.</li>
</ul>
<p><em>WRITE - Ctl</em></p>
<ul>
<li>0 = auto_enable - Defaults to ON after reset - Enables a
state machine that performs CMAC register writes to
bring up the MAC without SW intervention.</li>
<li>24:16 = pause_mask - A second layer of enables(the first being
register in the CMAC) on the pause_request mechanic. Bits
7:0 of enable pause on PFC7:0. Bit 8 enables global pause
request (not priority controlled). The mask is used for TX
and RX.</li>
</ul></div>
</div>
</div>
<div class="register">
<a name="NIXGE_REGMAP|MAC_PHY_STATUS"></a>
<h3 class="register">Offset 0x0008: MAC_PHY_STATUS Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('NIXGE_REGMAP|MAC_PHY_STATUS_in')">(<span id="show_NIXGE_REGMAP|MAC_PHY_STATUS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_NIXGE_REGMAP|MAC_PHY_STATUS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|NIXGE">QSFP_REGMAP|NIXGE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">MAC_PHY_STATUS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0008</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200008008
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200018008
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200028008
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200038008
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200048008
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200058008
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200068008
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200078008
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Definition of this register depends on Protocol</p>
<p><strong>10GBE</strong></p>
<p>*READ - Status *</p>
<ul>
<li>0 = core_status 0 - link_up</li>
<li>1 = core_status 1</li>
<li>2 = core_status 2</li>
<li>3 = core_status 3</li>
<li>4 = core_status 4</li>
<li>5 = core_status 5</li>
<li>6 = core_status 6</li>
<li>7 = core_status 7</li>
</ul>
<p><strong>100 GBE</strong></p>
<p><em>READ - Status</em></p>
<ul>
<li>0 = usr_tx_reset - TX PLL's have locked - The clock for the 100G mac isn't stable till this bit sets.</li>
<li>1 = usr_rx_reset - RX PLL's have locked</li>
</ul></div>
</div>
</div>
<div class="register">
<a name="NIXGE_REGMAP|MAC_LED_CTL"></a>
<h3 class="register">Offset 0x000C: MAC_LED_CTL Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('NIXGE_REGMAP|MAC_LED_CTL_in')">(<span id="show_NIXGE_REGMAP|MAC_LED_CTL_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_NIXGE_REGMAP|MAC_LED_CTL_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|NIXGE">QSFP_REGMAP|NIXGE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">MAC_LED_CTL</td></tr>
<tr><td class="offset_info" align="right"> offset=0x000C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000800C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001800C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002800C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003800C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004800C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005800C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006800C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007800C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..2</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">1</td>
<td>
<p><span class="name"><a name="NIXGE_REGMAP|MAC_LED_CTL|identify_value"></a>identify_value</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>When identify_enable is set, this value controls the activity LED.</p></div></p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="NIXGE_REGMAP|MAC_LED_CTL|identify_enable"></a>identify_enable</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>When set identify_value is used to control the activity LED.
When clear the activity LED set on any TX or RX traffic to the mgt</p></div></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="NIXGE_REGMAP|ETH_MDIO_BASE"></a>
<h3 class="register">Offset 0x0010: ETH_MDIO_BASE Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('NIXGE_REGMAP|ETH_MDIO_BASE_in')">(<span id="show_NIXGE_REGMAP|ETH_MDIO_BASE_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_NIXGE_REGMAP|ETH_MDIO_BASE_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|NIXGE">QSFP_REGMAP|NIXGE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">ETH_MDIO_BASE</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0010</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200008010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200018010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200028010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200038010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200048010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200058010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200068010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200078010
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>The x4xx family of products does not use MDIO.</p></div>
</div>
</div>
<div class="register">
<a name="NIXGE_REGMAP|AURORA_OVERRUNS"></a>
<h3 class="register">Offset 0x0020: AURORA_OVERRUNS Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('NIXGE_REGMAP|AURORA_OVERRUNS_in')">(<span id="show_NIXGE_REGMAP|AURORA_OVERRUNS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_NIXGE_REGMAP|AURORA_OVERRUNS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|NIXGE">QSFP_REGMAP|NIXGE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">AURORA_OVERRUNS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0020</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200008020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200018020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200028020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200038020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200048020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200058020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200068020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200078020
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Only valid if the protocol is Aurora.</p></div>
</div>
</div>
<div class="register">
<a name="NIXGE_REGMAP|AURORA_CHECKSUM_ERRORS"></a>
<h3 class="register">Offset 0x0024: AURORA_CHECKSUM_ERRORS Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('NIXGE_REGMAP|AURORA_CHECKSUM_ERRORS_in')">(<span id="show_NIXGE_REGMAP|AURORA_CHECKSUM_ERRORS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_NIXGE_REGMAP|AURORA_CHECKSUM_ERRORS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|NIXGE">QSFP_REGMAP|NIXGE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">AURORA_CHECKSUM_ERRORS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0024</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200008024
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200018024
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200028024
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200038024
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200048024
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200058024
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200068024
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200078024
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Only valid if the protocol is Aurora.</p></div>
</div>
</div>
<div class="register">
<a name="NIXGE_REGMAP|AURORA_BIST_CHECKER_SAMPS"></a>
<h3 class="register">Offset 0x0028: AURORA_BIST_CHECKER_SAMPS Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('NIXGE_REGMAP|AURORA_BIST_CHECKER_SAMPS_in')">(<span id="show_NIXGE_REGMAP|AURORA_BIST_CHECKER_SAMPS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_NIXGE_REGMAP|AURORA_BIST_CHECKER_SAMPS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|NIXGE">QSFP_REGMAP|NIXGE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">AURORA_BIST_CHECKER_SAMPS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0028</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200008028
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200018028
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200028028
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200038028
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200048028
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200058028
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200068028
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200078028
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Only valid if the protocol is Aurora.</p></div>
</div>
</div>
<div class="register">
<a name="NIXGE_REGMAP|AURORA_BIST_CHECKER_ERRORS"></a>
<h3 class="register">Offset 0x002C: AURORA_BIST_CHECKER_ERRORS Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('NIXGE_REGMAP|AURORA_BIST_CHECKER_ERRORS_in')">(<span id="show_NIXGE_REGMAP|AURORA_BIST_CHECKER_ERRORS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_NIXGE_REGMAP|AURORA_BIST_CHECKER_ERRORS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|NIXGE">QSFP_REGMAP|NIXGE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">AURORA_BIST_CHECKER_ERRORS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x002C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000802C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001802C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002802C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003802C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004802C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005802C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006802C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007802C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Only valid if the protocol is Aurora.</p></div>
</div>
</div>
</div>
<div class="group"><a name="NIXGE_REGMAP|XGE_MAC_WINDOW"></a><h2 class="group">XGE_MAC_WINDOW</h2>
<div class="xmlpmd">
</div>
<div class="register">
<a name="NIXGE_REGMAP|XGE_MAC"></a>
<h3 class="register">Offset 0x1000: XGE_MAC Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#XGE_MAC_REGMAP">XGE_MAC_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('NIXGE_REGMAP|XGE_MAC_in')">(<span id="show_NIXGE_REGMAP|XGE_MAC_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_NIXGE_REGMAP|XGE_MAC_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|NIXGE">QSFP_REGMAP|NIXGE</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">XGE_MAC</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1000</td></tr>
<tr><td class="offset_info" align="right"> size=0x1000 (4 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200009000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200019000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200029000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200039000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200049000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200059000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200069000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200079000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
</div>
</div>
<div class="regmap">
<a name="PL_CPLD_BASE_REGMAP"></a>
<h1 class="regmap">PL_CPLD_BASE_REGMAP</h1>
<div class="group"><a name="PL_CPLD_BASE_REGMAP|MB_CPLD_LED_REGS"></a><h2 class="group">MB_CPLD_LED_REGS</h2>
Register Map to control QSFP LEDs.
<div class="register">
<a name="PL_CPLD_BASE_REGMAP|LED_REGISTER"></a>
<h3 class="register">Offset 0x0020: LED_REGISTER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('PL_CPLD_BASE_REGMAP|LED_REGISTER_in')">(<span id="show_PL_CPLD_BASE_REGMAP|LED_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PL_CPLD_BASE_REGMAP|LED_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|PL_REGISTERS">MB_CPLD_PL_REGMAP|PL_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">LED_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0020</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088020
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file pl_cpld_regs.v.</p>
</div>
<div class="info">
Provides to the LEDs of the QSFP ports.
Write access will directly change the LED status.
The LED lights up if the corresponding bit is set.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|LED_REGISTER|QSFP1_LED_ACTIVE"></a>QSFP1_LED_ACTIVE</span><span class="attr"> </span></p>
<p>Active LEDs of QSFP port 1</p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..8</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|LED_REGISTER|QSFP1_LED_LINK"></a>QSFP1_LED_LINK</span><span class="attr"> </span></p>
<p>Link LEDs of QSFP port 1</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..4</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|LED_REGISTER|QSFP0_LED_ACTIVE"></a>QSFP0_LED_ACTIVE</span><span class="attr"> </span></p>
<p>Active LEDs of QSFP port 0</p>
</td>
</tr>
<tr valign="top">
<td class="bits">3..0</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|LED_REGISTER|QSFP0_LED_LINK"></a>QSFP0_LED_LINK</span><span class="attr"> </span></p>
<p>Link LEDs of QSFP port 0</p>
</td>
</tr>
</table>
</div>
</div>
<div class="group"><a name="PL_CPLD_BASE_REGMAP|PL_CMI_REGS"></a><h2 class="group">PL_CMI_REGS</h2>
Cable present status register.
<div class="register">
<a name="PL_CPLD_BASE_REGMAP|CABLE_PRESENT_REG"></a>
<h3 class="register">Offset 0x0030: CABLE_PRESENT_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('PL_CPLD_BASE_REGMAP|CABLE_PRESENT_REG_in')">(<span id="show_PL_CPLD_BASE_REGMAP|CABLE_PRESENT_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PL_CPLD_BASE_REGMAP|CABLE_PRESENT_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|PL_REGISTERS">MB_CPLD_PL_REGMAP|PL_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CABLE_PRESENT_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0030</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088030
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file pl_cpld_regs.v.</p>
</div>
<div class="info">
Information from FPGA about the cable present status.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">1</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|CABLE_PRESENT_REG|IPASS1_CABLE_PRESENT"></a>IPASS1_CABLE_PRESENT</span><span class="attr"> </span></p>
<p>Set to 1 if cable present in iPass 1 connector.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|CABLE_PRESENT_REG|IPASS0_CABLE_PRESENT"></a>IPASS0_CABLE_PRESENT</span><span class="attr"> </span></p>
<p>Set to 1 if cable present in iPass 0 connector.</p>
</td>
</tr>
</table>
</div>
</div>
<div class="group"><a name="PL_CPLD_BASE_REGMAP|PL_CPLD_BASE_REGS"></a><h2 class="group">PL_CPLD_BASE_REGS</h2>
Basic registers containing version and capabilities information.
<div class="register">
<a name="PL_CPLD_BASE_REGMAP|SIGNATURE_REGISTER"></a>
<h3 class="register">Offset 0x0000: SIGNATURE_REGISTER Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('PL_CPLD_BASE_REGMAP|SIGNATURE_REGISTER_in')">(<span id="show_PL_CPLD_BASE_REGMAP|SIGNATURE_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PL_CPLD_BASE_REGMAP|SIGNATURE_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|PL_REGISTERS">MB_CPLD_PL_REGMAP|PL_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SIGNATURE_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file pl_cpld_regs.v.</p>
</div>
<div class="info">
Contains the product's signature.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..0</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|SIGNATURE_REGISTER|PRODUCT_SIGNATURE"></a>PRODUCT_SIGNATURE</span><span class="attr"> </span></p>
<p>Fixed value PL_CPLD_SIGNATURE of <a href="#CONSTANTS_REGMAP">CONSTANTS_REGMAP</a></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="PL_CPLD_BASE_REGMAP|REVISION_REGISTER"></a>
<h3 class="register">Offset 0x0004: REVISION_REGISTER Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('PL_CPLD_BASE_REGMAP|REVISION_REGISTER_in')">(<span id="show_PL_CPLD_BASE_REGMAP|REVISION_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PL_CPLD_BASE_REGMAP|REVISION_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|PL_REGISTERS">MB_CPLD_PL_REGMAP|PL_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">REVISION_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0004</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088004
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file pl_cpld_regs.v.</p>
</div>
<div class="info">
Contains the CPLD revision (see CPLD_REVISION of <a href="#CONSTANTS_REGMAP">CONSTANTS_REGMAP</a>)
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|REVISION_REGISTER|REVISION_YY"></a>REVISION_YY</span><span class="attr"> </span></p>
<p>Contains revision year code.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|REVISION_REGISTER|REVISION_MM"></a>REVISION_MM</span><span class="attr"> </span></p>
<p>Contains revision month code.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|REVISION_REGISTER|REVISION_DD"></a>REVISION_DD</span><span class="attr"> </span></p>
<p>Contains revision day code.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..0</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|REVISION_REGISTER|REVISION_HH"></a>REVISION_HH</span><span class="attr"> </span></p>
<p>Contains revision hour code.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="PL_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER"></a>
<h3 class="register">Offset 0x0008: OLDEST_COMPATIBLE_REVISION_REGISTER Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('PL_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER_in')">(<span id="show_PL_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PL_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|PL_REGISTERS">MB_CPLD_PL_REGMAP|PL_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">OLDEST_COMPATIBLE_REVISION_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0008</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088008
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file pl_cpld_regs.v.</p>
</div>
<div class="info">
This register returns (in YYMMDDHH format) the oldest revision
that is still compatible with this one. Compatible means that
registers or register bits may have been added, but not
modified or deleted (see OLDEST_CPLD_REVISION of <a href="#CONSTANTS_REGMAP">CONSTANTS_REGMAP</a>).
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER|OLD_REVISION_YY"></a>OLD_REVISION_YY</span><span class="attr"> </span></p>
<p>Contains revision year code.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER|OLD_REVISION_MM"></a>OLD_REVISION_MM</span><span class="attr"> </span></p>
<p>Contains revision month code.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER|OLD_REVISION_DD"></a>OLD_REVISION_DD</span><span class="attr"> </span></p>
<p>Contains revision day code.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..0</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER|OLD_REVISION_HH"></a>OLD_REVISION_HH</span><span class="attr"> </span></p>
<p>Contains revision hour code.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="PL_CPLD_BASE_REGMAP|SCRATCH_REGISTER"></a>
<h3 class="register">Offset 0x000C: SCRATCH_REGISTER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('PL_CPLD_BASE_REGMAP|SCRATCH_REGISTER_in')">(<span id="show_PL_CPLD_BASE_REGMAP|SCRATCH_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PL_CPLD_BASE_REGMAP|SCRATCH_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|PL_REGISTERS">MB_CPLD_PL_REGMAP|PL_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SCRATCH_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x000C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x100008800C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file pl_cpld_regs.v.</p>
</div>
<div class="info">
Read/write register for general software use.
</div>
</div>
<div class="register">
<a name="PL_CPLD_BASE_REGMAP|GIT_HASH_REGISTER"></a>
<h3 class="register">Offset 0x0010: GIT_HASH_REGISTER Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('PL_CPLD_BASE_REGMAP|GIT_HASH_REGISTER_in')">(<span id="show_PL_CPLD_BASE_REGMAP|GIT_HASH_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PL_CPLD_BASE_REGMAP|GIT_HASH_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#PL_CPLD_REGMAP|MB_CPLD">PL_CPLD_REGMAP|MB_CPLD</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PL_REGMAP|PL_REGISTERS">MB_CPLD_PL_REGMAP|PL_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">GIT_HASH_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0010</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088010
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file pl_cpld_regs.v.</p>
</div>
<div class="info">
Git hash of commit used to build this image.<br>
Value equals 0xDEADBEEF if the git hash was not used during synthesis.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|GIT_HASH_REGISTER|GIT_CLEAN"></a>GIT_CLEAN</span><span class="attr"> </span></p>
<p>0x0 in case the git status was clean<br>
0xF in case there were uncommitted changes</p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..0</td>
<td>
<p><span class="name"><a name="PL_CPLD_BASE_REGMAP|GIT_HASH_REGISTER|GIT_HASH"></a>GIT_HASH</span><span class="attr"> </span></p>
<p>7 hex digit hash code of the commit</p>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="regmap">
<a name="PL_CPLD_REGMAP"></a>
<h1 class="regmap">PL_CPLD_REGMAP</h1>
This register map is available from the PS via AXI and MPM endpoint.
Its size is 128K (17 bits). Only the 17 LSBs are used as address in this documentation.
<div class="group"><a name="PL_CPLD_REGMAP|PL_CPLD_WINDOWS"></a><h2 class="group">PL_CPLD_WINDOWS</h2>
<div class="register">
<a name="PL_CPLD_REGMAP|BASE"></a>
<h3 class="register">Offset 0x0000: BASE Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#CPLD_INTERFACE_REGMAP">CPLD_INTERFACE_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('PL_CPLD_REGMAP|BASE_in')">(<span id="show_PL_CPLD_REGMAP|BASE_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PL_CPLD_REGMAP|BASE_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">BASE</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
<tr><td class="offset_info" align="right"> size=0x40 (64 bytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000080000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file cpld_interface.v.</p>
</div>
<div class="info">
</div>
</div>
<div class="register">
<a name="PL_CPLD_REGMAP|MB_CPLD"></a>
<h3 class="register">Offset 0x8000: MB_CPLD Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#MB_CPLD_PL_REGMAP">MB_CPLD_PL_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('PL_CPLD_REGMAP|MB_CPLD_in')">(<span id="show_PL_CPLD_REGMAP|MB_CPLD_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PL_CPLD_REGMAP|MB_CPLD_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">MB_CPLD</td></tr>
<tr><td class="offset_info" align="right"> offset=0x8000</td></tr>
<tr><td class="offset_info" align="right"> size=0x8000 (32 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000088000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file cpld_interface.v.</p>
</div>
<div class="info">
All registers of the MB CPLD (PL part).
</div>
</div>
<div class="register">
<a name="PL_CPLD_REGMAP|DB0_CPLD"></a>
<h3 class="register">Offset 0x10000: DB0_CPLD Window (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('PL_CPLD_REGMAP|DB0_CPLD_in')">(<span id="show_PL_CPLD_REGMAP|DB0_CPLD_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PL_CPLD_REGMAP|DB0_CPLD_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DB0_CPLD</td></tr>
<tr><td class="offset_info" align="right"> offset=0x10000</td></tr>
<tr><td class="offset_info" align="right"> size=0x8000 (32 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000090000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file cpld_interface.v.</p>
</div>
<div class="info">
All registers of the first DB CPLD. Register map will be added later on.
</div>
</div>
<div class="register">
<a name="PL_CPLD_REGMAP|DB1_CPLD"></a>
<h3 class="register">Offset 0x18000: DB1_CPLD Window (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('PL_CPLD_REGMAP|DB1_CPLD_in')">(<span id="show_PL_CPLD_REGMAP|DB1_CPLD_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PL_CPLD_REGMAP|DB1_CPLD_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|MPM_ENDPOINT">AXI_HPM0_REGMAP|MPM_ENDPOINT</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000080000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DB1_CPLD</td></tr>
<tr><td class="offset_info" align="right"> offset=0x18000</td></tr>
<tr><td class="offset_info" align="right"> size=0x8000 (32 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000098000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file cpld_interface.v.</p>
</div>
<div class="info">
All registers of the second DB CPLD. Register map will be added later on.
</div>
</div>
</div>
</div>
<div class="regmap">
<a name="PL_DMA_MASTER_REGMAP"></a>
<h1 class="regmap">PL_DMA_MASTER_REGMAP</h1>
This is a regmap to document the different ports that have access to the PS system memory.
Each port may have different restrictions on system memory. See the corresponding window
for details
<div class="group"><a name="PL_DMA_MASTER_REGMAP|HPC0_DMA"></a><h2 class="group">HPC0_DMA</h2>
<div class="register">
<a name="PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW"></a>
<h3 class="register">Offset 0x0000: AXI_HPC0_WINDOW Window (R|W)</h3>
<p class="offset_info"> Target port = <a href="#X4XX_FPGA|ARM_S_AXI_HPC0">X4XX_FPGA|ARM_S_AXI_HPC0</a></p>
<a class="sh_addrs" href="javascript:sa('PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW_in')">(<span id="show_PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">AXI_HPC0_WINDOW</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
<tr><td class="offset_info" align="right"> size=0x10000000000 (1024 Gbytes)</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
The HPC0 port of the PS is used for general purpose cache-coherent accesses
to the PS system memory. Different applications may use it for different
purposes. Its access is configured as follows: <br>
<table border="1">
<tr><th>Offset</th> <th>Size</th> <th>Description</th><tr>
<tr><td>0x000800000000</td><td>0x000800000000</td><td>DDR_HIGH</td><tr>
<tr><td>0x00000000</td> <td>0x80000000</td> <td>DDR_LOW</td><tr>
<tr><td>0xFF000000</td> <td>0x01000000</td> <td>LPS_OCM</td><tr>
<tr><td>0xC0000000</td> <td>0x20000000</td> <td>QSPI</td><tr>
</table>
</div>
</div>
</div>
<div class="group"><a name="PL_DMA_MASTER_REGMAP|HPC1_DMA"></a><h2 class="group">HPC1_DMA</h2>
<div class="register">
<a name="PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW"></a>
<h3 class="register">Offset 0x0000: AXI_HPC1_WINDOW Window (R|W)</h3>
<p class="offset_info"> Target port = <a href="#X4XX_FPGA|ARM_S_AXI_HPC1">X4XX_FPGA|ARM_S_AXI_HPC1</a></p>
<a class="sh_addrs" href="javascript:sa('PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW_in')">(<span id="show_PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">AXI_HPC1_WINDOW</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
<tr><td class="offset_info" align="right"> size=0x1000000000 (64 Gbytes)</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave
interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx.
Its access is configured as follows: <br>
<table border="1">
<tr><th>Offset</th> <th>Size</th> <th>Description</th><tr>
<tr><td>0x000800000000</td><td>0x000800000000</td><td>DDR_HIGH</td><tr>
<tr><td>0x00000000</td> <td>0x80000000</td> <td>DDR_LOW</td><tr>
<tr><td>0xC0000000</td> <td>0x20000000</td> <td>QSPI</td><tr>
</table>
</div>
</div>
</div>
</div>
<div class="regmap">
<a name="PS_CPLD_BASE_REGMAP"></a>
<h1 class="regmap">PS_CPLD_BASE_REGMAP</h1>
<div class="group"><a name="PS_CPLD_BASE_REGMAP|DIO_REGS"></a><h2 class="group">DIO_REGS</h2>
Registers to control the GPIO buffer direction on the DIO board connected to the FPGA.
Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers.
Set the direction in the FPGA's DIO register appropriately.
<div class="register">
<a name="PS_CPLD_BASE_REGMAP|DIO_DIRECTION_REGISTER"></a>
<h3 class="register">Offset 0x0030: DIO_DIRECTION_REGISTER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('PS_CPLD_BASE_REGMAP|DIO_DIRECTION_REGISTER_in')">(<span id="show_PS_CPLD_BASE_REGMAP|DIO_DIRECTION_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PS_CPLD_BASE_REGMAP|DIO_DIRECTION_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|PS_REGISTERS">MB_CPLD_PS_REGMAP|PS_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_DIRECTION_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0030</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000030
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file ps_cpld_regs.v.</p>
</div>
<div class="info">
Set the direction of FPGA buffer connected to DIO ports on the DIO board.<br/>
Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|DIO_DIRECTION_REGISTER|DIO_DIRECTION_B"></a>DIO_DIRECTION_B</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|DIO_DIRECTION_REGISTER|DIO_DIRECTION_A"></a>DIO_DIRECTION_A</span><span class="attr"> (initialvalue=0)</span></p>
<p></p>
</td>
</tr>
</table>
</div>
</div>
<div class="group"><a name="PS_CPLD_BASE_REGMAP|PS_CMI_REGS"></a><h2 class="group">PS_CMI_REGS</h2>
Cable present status register.
<div class="register">
<a name="PS_CPLD_BASE_REGMAP|SERIAL_NUM_LOW_REG"></a>
<h3 class="register">Offset 0x0034: SERIAL_NUM_LOW_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('PS_CPLD_BASE_REGMAP|SERIAL_NUM_LOW_REG_in')">(<span id="show_PS_CPLD_BASE_REGMAP|SERIAL_NUM_LOW_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PS_CPLD_BASE_REGMAP|SERIAL_NUM_LOW_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|PS_REGISTERS">MB_CPLD_PS_REGMAP|PS_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SERIAL_NUM_LOW_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0034</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000034
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ps_cpld_regs.v.</p>
</div>
<div class="info">
Least significant bytes of 5 byte serial number.
</div>
</div>
<div class="register">
<a name="PS_CPLD_BASE_REGMAP|SERIAL_NUM_HIGH_REG"></a>
<h3 class="register">Offset 0x0038: SERIAL_NUM_HIGH_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('PS_CPLD_BASE_REGMAP|SERIAL_NUM_HIGH_REG_in')">(<span id="show_PS_CPLD_BASE_REGMAP|SERIAL_NUM_HIGH_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PS_CPLD_BASE_REGMAP|SERIAL_NUM_HIGH_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|PS_REGISTERS">MB_CPLD_PS_REGMAP|PS_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SERIAL_NUM_HIGH_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0038</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000038
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ps_cpld_regs.v.</p>
</div>
<div class="info">
Most significant byte of 5 byte serial number.
</div>
</div>
<div class="register">
<a name="PS_CPLD_BASE_REGMAP|CMI_CONTROL_STATUS"></a>
<h3 class="register">Offset 0x003C: CMI_CONTROL_STATUS Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('PS_CPLD_BASE_REGMAP|CMI_CONTROL_STATUS_in')">(<span id="show_PS_CPLD_BASE_REGMAP|CMI_CONTROL_STATUS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PS_CPLD_BASE_REGMAP|CMI_CONTROL_STATUS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|PS_REGISTERS">MB_CPLD_PS_REGMAP|PS_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CMI_CONTROL_STATUS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x003C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00003C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ps_cpld_regs.v.</p>
</div>
<div class="info">
Control CMI communication and delivers information on the CMI link status.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31r</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|CMI_CONTROL_STATUS|OTHER_SIDE_DETECTED"></a>OTHER_SIDE_DETECTED</span><span class="attr"> </span></p>
<p>1 if an upstream CMI device has been detected.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">30..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..1</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|CMI_CONTROL_STATUS|CMI_READY"></a>CMI_READY</span><span class="attr"> </span></p>
<p>Set if the device is ready to establish a PCI-Express link (affects CMI_CLP_READY bit).</p>
</td>
</tr>
</table>
</div>
</div>
<div class="group"><a name="PS_CPLD_BASE_REGMAP|PS_CONTROL_REGS"></a><h2 class="group">PS_CONTROL_REGS</h2>
Register Map to control MB CPLD functions.
<div class="register">
<a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER"></a>
<h3 class="register">Offset 0x0020: PL_DB_REGISTER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('PS_CPLD_BASE_REGMAP|PL_DB_REGISTER_in')">(<span id="show_PS_CPLD_BASE_REGMAP|PL_DB_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PS_CPLD_BASE_REGMAP|PL_DB_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|PS_REGISTERS">MB_CPLD_PS_REGMAP|PS_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">PL_DB_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0020</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000020
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ps_cpld_regs.v.</p>
</div>
<div class="info">
Register to control the PL part DB SPI connection and reset generation.
The DB connection is clocked with PLL reference clock. Ensure this clock is stable
and enabled before starting any SPI request.
The PLL reference clock can be disabled if both DB connections are disabled or inactive.
To enable the DB connection, enable clock with one write access and release
reset with the next write access.
To disable the DB connection, assert reset with one write access and
disable clocks with the next write access.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..22</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">21w</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|ASSERT_RESET_DB1"></a>ASSERT_RESET_DB1</span><span class="attr"> </span></p>
<p>Writing with this flag set asserts reset for DB 1 (overrides <a href="#PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|RELEASE_RESET_DB1">RELEASE_RESET_DB1</a>)</p>
</td>
</tr>
<tr valign="top">
<td class="bits">20w</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|ASSERT_RESET_DB0"></a>ASSERT_RESET_DB0</span><span class="attr"> </span></p>
<p>Writing with this flag set asserts reset for DB 0 (overrides <a href="#PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|RELEASE_RESET_DB0">RELEASE_RESET_DB0</a>)</p>
</td>
</tr>
<tr valign="top">
<td class="bits">19..18</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">17w</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|RELEASE_RESET_DB1"></a>RELEASE_RESET_DB1</span><span class="attr"> </span></p>
<p>Writing with this flag set releases DB 1 reset. (may be overwritten by <a href="#PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|ASSERT_RESET_DB1">ASSERT_RESET_DB1</a>)</p>
</td>
</tr>
<tr valign="top">
<td class="bits">16w</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|RELEASE_RESET_DB0"></a>RELEASE_RESET_DB0</span><span class="attr"> </span></p>
<p>Writing with this flag set releases DB 0 reset. (may be overwritten by <a href="#PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|ASSERT_RESET_DB0">ASSERT_RESET_DB0</a>)</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">14w</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|DISABLE_PLL_REF_CLOCK"></a>DISABLE_PLL_REF_CLOCK</span><span class="attr"> </span></p>
<p>Writing with this flag set disables the PLL reference clock (overrides <a href="#PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|ENABLE_PLL_REF_CLOCK">ENABLE_PLL_REF_CLOCK</a>). Assert this flag to reconfigure the clock.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">13w</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|DISABLE_CLOCK_DB1"></a>DISABLE_CLOCK_DB1</span><span class="attr"> </span></p>
<p>Writing with this flag set disables DB 1 clock forwarding (overrides <a href="#PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|ENABLE_CLOCK_DB1">ENABLE_CLOCK_DB1</a>)</p>
</td>
</tr>
<tr valign="top">
<td class="bits">12w</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|DISABLE_CLOCK_DB0"></a>DISABLE_CLOCK_DB0</span><span class="attr"> </span></p>
<p>Writing with this flag set disables DB 0 clock forwarding (overrides <a href="#PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|ENABLE_CLOCK_DB0">ENABLE_CLOCK_DB0</a>)</p>
</td>
</tr>
<tr valign="top">
<td class="bits">11</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">10w</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|ENABLE_PLL_REF_CLOCK"></a>ENABLE_PLL_REF_CLOCK</span><span class="attr"> </span></p>
<p>Writing with this flag set enables the PLL reference clock. Assert this flag after PLL reference clock is stable. (may be overwritten by <a href="#PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|DISABLE_PLL_REF_CLOCK">DISABLE_PLL_REF_CLOCK</a>)</p>
</td>
</tr>
<tr valign="top">
<td class="bits">9w</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|ENABLE_CLOCK_DB1"></a>ENABLE_CLOCK_DB1</span><span class="attr"> </span></p>
<p>Writing with this flag set enables DB 1 clock forwarding. (may be overwritten by <a href="#PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|DISABLE_CLOCK_DB1">DISABLE_CLOCK_DB1</a>)</p>
</td>
</tr>
<tr valign="top">
<td class="bits">8w</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|ENABLE_CLOCK_DB0"></a>ENABLE_CLOCK_DB0</span><span class="attr"> </span></p>
<p>Writing with this flag set enables DB 0 clock forwarding. (may be overwritten by <a href="#PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|DISABLE_CLOCK_DB0">DISABLE_CLOCK_DB0</a>)</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..6</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">5r</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|DB1_RESET_ASSERTED"></a>DB1_RESET_ASSERTED</span><span class="attr"> </span></p>
<p>Indicates that reset is asserted for DB 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">4r</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|DB0_RESET_ASSERTED"></a>DB0_RESET_ASSERTED</span><span class="attr"> </span></p>
<p>Indicates that reset is asserted for DB 0.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">3</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">2r</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|PLL_REF_CLOCK_ENABLED"></a>PLL_REF_CLOCK_ENABLED</span><span class="attr"> </span></p>
<p>Indicates if the PLL reference clock for the PL interface is enabled.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">1r</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|DB1_CLOCK_ENABLED"></a>DB1_CLOCK_ENABLED</span><span class="attr"> </span></p>
<p>Indicates if a clock is forwarded to DB 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">0r</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|PL_DB_REGISTER|DB0_CLOCK_ENABLED"></a>DB0_CLOCK_ENABLED</span><span class="attr"> </span></p>
<p>Indicates if a clock is forwarded to DB 0.</p>
</td>
</tr>
</table>
</div>
</div>
<div class="group"><a name="PS_CPLD_BASE_REGMAP|PS_CPLD_BASE_REGS"></a><h2 class="group">PS_CPLD_BASE_REGS</h2>
Basic registers containing version and capabilites information.
<div class="register">
<a name="PS_CPLD_BASE_REGMAP|SIGNATURE_REGISTER"></a>
<h3 class="register">Offset 0x0000: SIGNATURE_REGISTER Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('PS_CPLD_BASE_REGMAP|SIGNATURE_REGISTER_in')">(<span id="show_PS_CPLD_BASE_REGMAP|SIGNATURE_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PS_CPLD_BASE_REGMAP|SIGNATURE_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|PS_REGISTERS">MB_CPLD_PS_REGMAP|PS_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SIGNATURE_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ps_cpld_regs.v.</p>
</div>
<div class="info">
Contains the product's signature.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..0</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|SIGNATURE_REGISTER|PRODUCT_SIGNATURE"></a>PRODUCT_SIGNATURE</span><span class="attr"> </span></p>
<p>Fixed value PS_CPLD_SIGNATURE of <a href="#CONSTANTS_REGMAP">CONSTANTS_REGMAP</a></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="PS_CPLD_BASE_REGMAP|REVISION_REGISTER"></a>
<h3 class="register">Offset 0x0004: REVISION_REGISTER Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('PS_CPLD_BASE_REGMAP|REVISION_REGISTER_in')">(<span id="show_PS_CPLD_BASE_REGMAP|REVISION_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PS_CPLD_BASE_REGMAP|REVISION_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|PS_REGISTERS">MB_CPLD_PS_REGMAP|PS_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">REVISION_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0004</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000004
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ps_cpld_regs.v.</p>
</div>
<div class="info">
Contains the CPLD revision (see CPLD_REVISION of <a href="#CONSTANTS_REGMAP">CONSTANTS_REGMAP</a>).
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|REVISION_REGISTER|REVISION_YY"></a>REVISION_YY</span><span class="attr"> </span></p>
<p>Contains revision year code.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|REVISION_REGISTER|REVISION_MM"></a>REVISION_MM</span><span class="attr"> </span></p>
<p>Contains revision month code.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|REVISION_REGISTER|REVISION_DD"></a>REVISION_DD</span><span class="attr"> </span></p>
<p>Contains revision day code.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..0</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|REVISION_REGISTER|REVISION_HH"></a>REVISION_HH</span><span class="attr"> </span></p>
<p>Contains revision hour code.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="PS_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER"></a>
<h3 class="register">Offset 0x0008: OLDEST_COMPATIBLE_REVISION_REGISTER Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('PS_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER_in')">(<span id="show_PS_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PS_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|PS_REGISTERS">MB_CPLD_PS_REGMAP|PS_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">OLDEST_COMPATIBLE_REVISION_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0008</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000008
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ps_cpld_regs.v.</p>
</div>
<div class="info">
This register returns (in YYMMDDHH format) the oldest revision
that is still compatible with this one. Compatible means that
registers or register bits may have been added, but not
modified or deleted (see OLDEST_CPLD_REVISION of <a href="#CONSTANTS_REGMAP">CONSTANTS_REGMAP</a>).
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER|OLD_REVISION_YY"></a>OLD_REVISION_YY</span><span class="attr"> </span></p>
<p>Contains revision year code.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER|OLD_REVISION_MM"></a>OLD_REVISION_MM</span><span class="attr"> </span></p>
<p>Contains revision month code.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER|OLD_REVISION_DD"></a>OLD_REVISION_DD</span><span class="attr"> </span></p>
<p>Contains revision day code.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..0</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER|OLD_REVISION_HH"></a>OLD_REVISION_HH</span><span class="attr"> </span></p>
<p>Contains revision hour code.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="PS_CPLD_BASE_REGMAP|SCRATCH_REGISTER"></a>
<h3 class="register">Offset 0x000C: SCRATCH_REGISTER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('PS_CPLD_BASE_REGMAP|SCRATCH_REGISTER_in')">(<span id="show_PS_CPLD_BASE_REGMAP|SCRATCH_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PS_CPLD_BASE_REGMAP|SCRATCH_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|PS_REGISTERS">MB_CPLD_PS_REGMAP|PS_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SCRATCH_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x000C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00000C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ps_cpld_regs.v.</p>
</div>
<div class="info">
Read/write register for general software use.
</div>
</div>
<div class="register">
<a name="PS_CPLD_BASE_REGMAP|GIT_HASH_REGISTER"></a>
<h3 class="register">Offset 0x0010: GIT_HASH_REGISTER Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('PS_CPLD_BASE_REGMAP|GIT_HASH_REGISTER_in')">(<span id="show_PS_CPLD_BASE_REGMAP|GIT_HASH_REGISTER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PS_CPLD_BASE_REGMAP|GIT_HASH_REGISTER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|PS_REGISTERS">MB_CPLD_PS_REGMAP|PS_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">GIT_HASH_REGISTER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0010</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000010
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ps_cpld_regs.v.</p>
</div>
<div class="info">
Git hash of commit used to build this image.<br>
Value equals 0xDEADBEEF if the git hash was not used during synthesis.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|GIT_HASH_REGISTER|GIT_CLEAN"></a>GIT_CLEAN</span><span class="attr"> </span></p>
<p>0x0 in case the git status was clean<br>
0xF in case there were uncommitted changes</p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..0</td>
<td>
<p><span class="name"><a name="PS_CPLD_BASE_REGMAP|GIT_HASH_REGISTER|GIT_HASH"></a>GIT_HASH</span><span class="attr"> </span></p>
<p>7 hex digit hash code of the commit</p>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="regmap">
<a name="PS_POWER_REGMAP"></a>
<h1 class="regmap">PS_POWER_REGMAP</h1>
<div class="group"><a name="PS_POWER_REGMAP|PS_POWER_REGS"></a><h2 class="group">PS_POWER_REGS</h2>
Registers to control power supplies on the motherboard.
<div class="register">
<a name="PS_POWER_REGMAP|IPASS_POWER_REG"></a>
<h3 class="register">Offset 0x0000: IPASS_POWER_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('PS_POWER_REGMAP|IPASS_POWER_REG_in')">(<span id="show_PS_POWER_REGMAP|IPASS_POWER_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PS_POWER_REGMAP|IPASS_POWER_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|POWER_REGISTERS">MB_CPLD_PS_REGMAP|POWER_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000060</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">IPASS_POWER_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000060
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ps_power_regs.v.</p>
</div>
<div class="info">
Controls the power supplies for the iPass connectors.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31r</td>
<td>
<p><span class="name"><a name="PS_POWER_REGMAP|IPASS_POWER_REG|IPASS_POWER_FAULT1"></a>IPASS_POWER_FAULT1</span><span class="attr"> </span></p>
<p>Asserted signal indicates a power fault in power switch for iPass
connector 1. Sticky bit. Asserted on occurrence. Reset using
<a href="#PS_POWER_REGMAP|IPASS_POWER_REG|IPASS_CLEAR_POWER_FAULT1">IPASS_CLEAR_POWER_FAULT1</a>.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">31w</td>
<td>
<p><span class="name"><a name="PS_POWER_REGMAP|IPASS_POWER_REG|IPASS_CLEAR_POWER_FAULT1"></a>IPASS_CLEAR_POWER_FAULT1</span><span class="attr"> </span></p>
<p>Clear <a href="#PS_POWER_REGMAP|IPASS_POWER_REG|IPASS_POWER_FAULT1">IPASS_POWER_FAULT1</a>.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">30r</td>
<td>
<p><span class="name"><a name="PS_POWER_REGMAP|IPASS_POWER_REG|IPASS_POWER_FAULT0"></a>IPASS_POWER_FAULT0</span><span class="attr"> </span></p>
<p>Asserted signal indicates a power fault in power switch for iPass
connector 0. Sticky bit. Asserted on occurrence. Reset using
<a href="#PS_POWER_REGMAP|IPASS_POWER_REG|IPASS_CLEAR_POWER_FAULT0">IPASS_CLEAR_POWER_FAULT0</a>.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">30w</td>
<td>
<p><span class="name"><a name="PS_POWER_REGMAP|IPASS_POWER_REG|IPASS_CLEAR_POWER_FAULT0"></a>IPASS_CLEAR_POWER_FAULT0</span><span class="attr"> </span></p>
<p>Clear <a href="#PS_POWER_REGMAP|IPASS_POWER_REG|IPASS_POWER_FAULT0">IPASS_POWER_FAULT0</a>.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">29..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..1</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="PS_POWER_REGMAP|IPASS_POWER_REG|IPASS_DISABLE_POWER_BIT"></a>IPASS_DISABLE_POWER_BIT</span><span class="attr"> </span></p>
<p>Set to 1 to disable power for both iPass connectors.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="PS_POWER_REGMAP|OSC_POWER_REG"></a>
<h3 class="register">Offset 0x0004: OSC_POWER_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('PS_POWER_REGMAP|OSC_POWER_REG_in')">(<span id="show_PS_POWER_REGMAP|OSC_POWER_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_PS_POWER_REGMAP|OSC_POWER_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|POWER_REGISTERS">MB_CPLD_PS_REGMAP|POWER_REGISTERS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000060</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">OSC_POWER_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0004</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000064
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ps_power_regs.v.</p>
</div>
<div class="info">
Controls the power supplies for the oscillators.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..2</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">1</td>
<td>
<p><span class="name"><a name="PS_POWER_REGMAP|OSC_POWER_REG|OSC_122_88"></a>OSC_122_88</span><span class="attr"> </span></p>
<p>Enables 5V power switch for the 122.88 MHz oscillator.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="PS_POWER_REGMAP|OSC_POWER_REG|OSC_100"></a>OSC_100</span><span class="attr"> </span></p>
<p>Enables 5V power switch for the 100 MHz oscillator.</p>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="regmap">
<a name="QSFP_REGMAP"></a>
<h1 class="regmap">QSFP_REGMAP</h1>
<div class="xmlpmd">
</div>
<div class="group"><a name="QSFP_REGMAP|QSFP_WINDOWS"></a><h2 class="group">QSFP_WINDOWS</h2>
<div class="xmlpmd">
<p>Register space for a single QSFP Communication port. This currently breaks into 2 possible configurations</p>
<ul>
<li>1X10GB Ethernet - Using OpenCore XGE MAC</li>
<li>1x100GB Ethernet - Using Xilinx CMAC</li>
<li>(future possible) - Xilinx Aurora (various rates and lane widths)</li>
<li>(future possible) - 4X10GB Ethernet</li>
</ul></div>
<div class="register">
<a name="QSFP_REGMAP|ETH_DMA"></a>
<h3 class="register">Offset 0x0000: ETH_DMA Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#DMA_REGMAP">DMA_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('QSFP_REGMAP|ETH_DMA_in')">(<span id="show_QSFP_REGMAP|ETH_DMA_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_QSFP_REGMAP|ETH_DMA_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">ETH_DMA</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
<tr><td class="offset_info" align="right"> size=0x4000 (16 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200000000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200010000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200020000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200030000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200040000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200050000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200060000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200070000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
<div class="register">
<a name="QSFP_REGMAP|NIXGE"></a>
<h3 class="register">Offset 0x8000: NIXGE Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#NIXGE_REGMAP">NIXGE_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('QSFP_REGMAP|NIXGE_in')">(<span id="show_QSFP_REGMAP|NIXGE_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_QSFP_REGMAP|NIXGE_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">NIXGE</td></tr>
<tr><td class="offset_info" align="right"> offset=0x8000</td></tr>
<tr><td class="offset_info" align="right"> size=0x2000 (8 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200008000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200018000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200028000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200038000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200048000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200058000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200068000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1200078000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
<div class="register">
<a name="QSFP_REGMAP|UIO"></a>
<h3 class="register">Offset 0xA000: UIO Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#UIO_REGMAP">UIO_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('QSFP_REGMAP|UIO_in')">(<span id="show_QSFP_REGMAP|UIO_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_QSFP_REGMAP|UIO_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">UIO</td></tr>
<tr><td class="offset_info" align="right"> offset=0xA000</td></tr>
<tr><td class="offset_info" align="right"> size=0x2000 (8 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007A000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
<div class="register">
<a name="QSFP_REGMAP|CMAC"></a>
<h3 class="register">Offset 0xC000: CMAC Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#CMAC_REGMAP">CMAC_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('QSFP_REGMAP|CMAC_in')">(<span id="show_QSFP_REGMAP|CMAC_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_QSFP_REGMAP|CMAC_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CMAC</td></tr>
<tr><td class="offset_info" align="right"> offset=0xC000</td></tr>
<tr><td class="offset_info" align="right"> size=0x2000 (8 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000C000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001C000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002C000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003C000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004C000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005C000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006C000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007C000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
</div>
</div>
</div>
<div class="regmap">
<a name="RADIO_CTRLPORT_REGMAP"></a>
<h1 class="regmap">RADIO_CTRLPORT_REGMAP</h1>
<div class="group"><a name="RADIO_CTRLPORT_REGMAP|RADIO_CTRLPORT_WINDOWS"></a><h2 class="group">RADIO_CTRLPORT_WINDOWS</h2>
Each radio's CtrlPort peripheral interface is divided into the
following memory spaces. Note that the CtrlPort peripheral interface
starts at offset 0x80000 in the RFNoC Radio block's register space.
The following diagram displays the distribution of the CtrlPort
interface to the different modules it interacts with.
<img src = "x4xx_core_common_buses.svg"
<div class="register">
<a name="RADIO_CTRLPORT_REGMAP|DB_WINDOW"></a>
<h3 class="register">Offset 0x0000: DB_WINDOW Window (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('RADIO_CTRLPORT_REGMAP|DB_WINDOW_in')">(<span id="show_RADIO_CTRLPORT_REGMAP|DB_WINDOW_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RADIO_CTRLPORT_REGMAP|DB_WINDOW_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DB_WINDOW</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
<tr><td class="offset_info" align="right"> size=0x8000 (32 Kbytes)</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
<div class="info">
Daughterboard GPIO interface. Register access within this space
is directed to the associated daughterboard CPLD.
</div>
</div>
<div class="register">
<a name="RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW"></a>
<h3 class="register">Offset 0x8000: RFDC_TIMING_WINDOW Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#RFDC_TIMING_REGMAP">RFDC_TIMING_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW_in')">(<span id="show_RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RFDC_TIMING_WINDOW</td></tr>
<tr><td class="offset_info" align="right"> offset=0x8000</td></tr>
<tr><td class="offset_info" align="right"> size=0x4000 (16 Kbytes)</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
<div class="info">
RFDC timing control interface.
</div>
</div>
<div class="register">
<a name="RADIO_CTRLPORT_REGMAP|DIO_WINDOW"></a>
<h3 class="register">Offset 0xC000: DIO_WINDOW Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#RADIO_DIO_REGMAP">RADIO_DIO_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('RADIO_CTRLPORT_REGMAP|DIO_WINDOW_in')">(<span id="show_RADIO_CTRLPORT_REGMAP|DIO_WINDOW_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RADIO_CTRLPORT_REGMAP|DIO_WINDOW_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_WINDOW</td></tr>
<tr><td class="offset_info" align="right"> offset=0xC000</td></tr>
<tr><td class="offset_info" align="right"> size=0x4000 (16 Kbytes)</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
<div class="info">
DIO control interface. Interacts with the DIO source selection
block, ATR-based DIO control and the DIO digital interface
</div>
</div>
</div>
</div>
<div class="regmap">
<a name="RADIO_DIO_REGMAP"></a>
<h1 class="regmap">RADIO_DIO_REGMAP</h1>
This map contains register windows for controlling the different sources
that drive the state of DIO lines.
<div class="group"><a name="RADIO_DIO_REGMAP|DIO_SOURCES"></a><h2 class="group">DIO_SOURCES</h2>
<div class="register">
<a name="RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS"></a>
<h3 class="register">Offset 0x0000: RADIO_GPIO_ATR_REGS Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#GPIO_ATR_REGMAP">GPIO_ATR_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS_in')">(<span id="show_RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RADIO_GPIO_ATR_REGS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
<tr><td class="offset_info" align="right"> size=0x1000 (4 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00C000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
<div class="info">
Contains controls for DIO behavior based on the ATR state of the accessed radio
</div>
</div>
<div class="register">
<a name="RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL"></a>
<h3 class="register">Offset 0x1000: DIO_SOURCE_CONTROL Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#DIO_REGMAP">DIO_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL_in')">(<span id="show_RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_SOURCE_CONTROL</td></tr>
<tr><td class="offset_info" align="right"> offset=0x1000</td></tr>
<tr><td class="offset_info" align="right"> size=0x1000 (4 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00D000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
<div class="info">
Window to access the DIO register map through the control port from the radio blocks.
</div>
</div>
<div class="register">
<a name="RADIO_DIO_REGMAP|DIGITAL_IFC_REGS"></a>
<h3 class="register">Offset 0x2000: DIGITAL_IFC_REGS Window (R|W)</h3>
<p class="offset_info"> Target regmap = <a href="#DIG_IFC_REGMAP">DIG_IFC_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('RADIO_DIO_REGMAP|DIGITAL_IFC_REGS_in')">(<span id="show_RADIO_DIO_REGMAP|DIGITAL_IFC_REGS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RADIO_DIO_REGMAP|DIGITAL_IFC_REGS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIGITAL_IFC_REGS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x2000</td></tr>
<tr><td class="offset_info" align="right"> size=0x1000 (4 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00E000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
<div class="info">
Register space reserved for configuring a digital interface over the GPIO lines.
Currently, SPI is the only supported protocol.
</div>
</div>
</div>
</div>
<div class="regmap">
<a name="RECONFIG_REGMAP"></a>
<h1 class="regmap">RECONFIG_REGMAP</h1>
<div class="group"><a name="RECONFIG_REGMAP|RECONFIG_REGS"></a><h2 class="group">RECONFIG_REGS</h2>
These registers are used to upload and verify a new primary image to the
Max 10 FPGA on-chip flash when configured to support dual configuration
images. The steps below outline the process of verifying/preparing the
new image to be written, erasing the current image, writing the new
image, and verifying the new image was successfully written.
<p><b>Prepare the data...</b>
<ol><li><p>The Max 10 FPGA build should generate a *cfm0_auto.rpd
file The *.rpd file is a "raw programming
data" file holding all data related to the
configuration image (CFM0). There are two
important items to note regarding the addresses.
First the *rpd data uses <b>byte</b> addresses.
Second, the start/end addresses defined by
FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses</p></li>
<li><p>As a sanity check, verify the size of the raw
programming data for CFM0 correspond to the address
range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by
reading the values from FLASH_CFM0_START_ADDR_REG and
FLASH_CFM0_END_ADDR, subtract both values, add one and
multiply by four.
</p></li>
<li><p>Having passed the sanity check the *.rpd data must
now be manipulated into the form required by Altera's
on-chip flash IP. Two operations must be performed.
First the data must be converted from bytes to 32-bit
words. Second the bit order must be reversed. This is
illustrated in in the following table which shows byte
address and data from the *.rpd file compared to the
word address and data to be written to the on-chip
flash.
<table border=1>
<tr><td>.Map Addr</td><td>.Map Data</td><td>Flash Addr</td><td>Flash Data</td></tr>
<tr><td>0x2B800</td><td>0x01</td><td rowspan=4>0xAC00</td><td rowspan=4>0x8040C020</td></tr>
<tr><td>0x2B801</td><td>0x02</td></tr>
<tr><td>0x2B802</td><td>0x03</td></tr>
<tr><td>0x2B803</td><td>0x04</td></tr>
<tr><td>0x2B804</td><td>0x05</td><td rowspan=4>0xAC01</td><td rowspan=4>0xA060E010</td></tr>
<tr><td>0x2B805</td><td>0x06</td></tr>
<tr><td>0x2B806</td><td>0x07</td></tr>
<tr><td>0x2B807</td><td>0x08</td></tr>
</table>
</p></li>
<li><p>The resulting set of flash address data pairs should
be used when writing FLASH_ADDR_REG and
FLASH_WRITE_DATA_REG to update the CFM0 image.
However, prior to writing the new image the old image
must be erased.
</p></li>
</ol>
</p>
<p><b>Erase the current primary flash image...</b>
<ol><p><li>Read FLASH_STATUS_REG and verify no error bits are
asserted and that all read, write, and erase operations
are idle.</p></li>
<p><li>Disable write protection of the flash by strobing the
FLASH_DISABLE_WP_STB bit of FLASH_CONTROL_REG.
</p></li>
<p><li>Verify write protection is disabled and no errors are
present by reading FLASH_STATUS_REG.</p></li>
<p><li>Initiate the erase operation by setting
<a href="#RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_SECTOR">FLASH_ERASE_SECTOR</a> and strobing FLASH_ERASE_STB of
FLASH_CONTROL_REG.</p></li>
<p><li>Poll the FLASH_ERASE_IDLE bit of
FLASH_STATUS_REG until it de-asserts indicating the
erase operation is complete, then verify the operation
was successful by checking that the FLASH_ERASE_ERR
bit is de-asserted. Erase operations are expected to
take a maximum of 350 msec. Upon completion of the erase
operation write protection will remain disabled.
</p></li>
<p><li>Erase additional sectors as required (see
<a href="#RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_SECTOR">FLASH_ERASE_SECTOR</a> for details) by restarting with first
step.</p></li>
</ol>
</p>
<p><b>Write the new primary flash image...</b>
<ol><p><li>Read FLASH_STATUS_REG and verify no error bits are
asserted, all read, write, and erase operations are
idle, and write protection is disabled.</li>
<p><li>Set the target address for the write to the Max 10
on-chip flash by writing value from
FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.</li></p>
<p><li>Set the data to be written to this address by writing
the new 32-bit word of the new image to
FLASH_WRITE_DATA_REG.</li></p>
<p><li>Initiate the write by strobing FLASH_WRITE_STB of
FLASH_CONTROL_REG.</li></p>
<p><li>Poll the FLASH_WRITE_IDLE bit of
FLASH_STATUS_REG until it de-asserts indicating the
write operation is complete, then verify the operation
was successful by checking that the FLASH_WRITE_ERR
bit is de-asserted. Write operations are expected to
take a maximum of 550 usec.</li></p>
<p><li>Upon completion of the write operation return to step
2, incrementing the target address by one, and writing
the next 32-bit word to Max10FlashWriteDatReg. If this
was the last write, indicated by writing to
FLASH_PRIMARY_IMAGE_END_ADDR, proceed to the next step
to enable write protection.</li></p>
<p><li>After writing the new image enable write protection
by strobing the FLASH_ENABLE_WP_STB bit of
FLASH_CONTROL_REG.</li></p>
</ol>
</p>
<p><b>Verify the new primary flash image...</b>
<ol><p><li>Read FLASH_STATUS_REG and verify no error bits are
asserted and that all read, write, and erase operations
are idle.</li></p>
<p><li>Set the target address for the read in the Max 10
on-chip flash by writing value from
FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.</li></p>
<p><li>Initiate the read by strobing FLASH_READ_STB of
FLASH_CONTROL_REG.</li></p>
<p><li>Poll the FLASH_READ_IDLE bit of
FLASH_STATUS_REG until it de-asserts indicating the
read operation is complete, then verify the operation
was successful by checking that the FLASH_READ_ERR
bit is de-asserted. There is no guidance on exactly how
long reads take to complete, but they are expected to be
fairly quick. A very conservative timeout on this
polling would be similar to that used for write
operations.</li></p>
<p><li>Upon completion of the read operation the resulting
data returned by the on-chip flash will be available in
Max10FlashReadDatReg. Read this register, compare to
expected value previously written, and ensure they
match.</li></p>
<p><li>Return to step 2, incrementing the target
address by one. If this was the last read verification
is complete and no further action is required.</li></p>
</ol>
</p>
<p>After the flash has been erased, programmed, and verified, a power
cycle is required for the new image to become active.
</p>
<div class="enum">
<a name="RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM"></a>
<h3 class="enum">FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration</h3>
These values are the start and end address of the CFM image flash
sector from Intel's On-Chip Flash IP Generator.
Be aware that three different values exist per each of the two
supported MAX10 variants: 10M04 and 10M08
Note that the values given in the IP generator are byte based where
the values of this enum are U32 based (divided by 4).
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' colspan='2'> Value </td>
<td class="l" rowspan='2' colspan='1'> Name </td>
</tr>
<tr class="header2" valign="bottom">
<td class='value'> Dec </td>
<td class='l'> Hex </td>
</tr>
<tr valign="top">
<td class='value'>4096</td>
<td class='l'>0x01000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04</p>
</td>
</tr>
<tr valign="top">
<td class='value'>8192</td>
<td class='l'>0x02000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08</p>
</td>
</tr>
<tr valign="top">
<td class='value'>39936</td>
<td class='l'>0x09C00</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_10M04'></a>FLASH_PRIMARY_IMAGE_START_ADDR_10M04</p>
</td>
</tr>
<tr valign="top">
<td class='value'>44032</td>
<td class='l'>0x0AC00</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_10M08'></a>FLASH_PRIMARY_IMAGE_START_ADDR_10M08</p>
</td>
</tr>
<tr valign="top">
<td class='value'>75775</td>
<td class='l'>0x127FF</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR_10M04'></a>FLASH_PRIMARY_IMAGE_END_ADDR_10M04</p>
</td>
</tr>
<tr valign="top">
<td class='value'>79871</td>
<td class='l'>0x137FF</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR_10M08'></a>FLASH_PRIMARY_IMAGE_END_ADDR_10M08</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file reconfig_engine.v.
</p>
</div>
<div class="register">
<a name="RECONFIG_REGMAP|FLASH_STATUS_REG"></a>
<h3 class="register">Offset 0x0000: FLASH_STATUS_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_STATUS_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_STATUS_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_STATUS_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|RECONFIG">MB_CPLD_PS_REGMAP|RECONFIG</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000040</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">FLASH_STATUS_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000040
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>
</div>
<div class="info">
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..17</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">16</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_MEM_INIT_ENABLED"></a>FLASH_MEM_INIT_ENABLED</span><span class="attr"> </span></p>
<p>This bit is asserted when the flash can hold an image with memory
initialization.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..14</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">13</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_WRITE_ERR"></a>FLASH_WRITE_ERR</span><span class="attr"> </span></p>
<p>This bit is asserted when write operation fails. Clear this error
by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In
the event of a write error...
<li><b>the primary configuration image may be corrupted,</b> and
power cycling the board may result unknown behavior.</li>
<li>write protection of the flash will automatically be
re-enabled.</li>
<li>attempts to disable write protection will be ignored.</li>
<li>attempts to read/write/erase the flash will be ignored.</li></p>
</td>
</tr>
<tr valign="top">
<td class="bits">12</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_WRITE_IDLE"></a>FLASH_WRITE_IDLE</span><span class="attr"> </span></p>
<p>This bit is de-asserted when a write operation is in progress. Poll
this bit after strobing the FLASH_WRITE_STB bit of
FLASH_CONTROL_REG to determine when the write operation has
completed, then check the FLASH_WRITE_ERR bit to verify the
operation was successful.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..10</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">9</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_ERASE_ERR"></a>FLASH_ERASE_ERR</span><span class="attr"> </span></p>
<p>This bit is asserted when an erase operation fails. Clear this
error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In
the event of an erase error...
<li><b>the primary configuration image may be corrupted,</b> and
power cycling the board may result in unknown behavior.</li>
<li>write protection of the flash will automatically be
re-enabled.</li>
<li>attempts to disable write protection will be ignored.</li>
<li>attempts to read/write/erase the flash will be ignored.</li></p>
</td>
</tr>
<tr valign="top">
<td class="bits">8</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_ERASE_IDLE"></a>FLASH_ERASE_IDLE</span><span class="attr"> </span></p>
<p>This bit is de-asserted when an erase operation is in progress. Poll
this bit after strobing the FLASH_ERASE_STB bit of
FLASH_CONTROL_REG to determine when the erase operation has
completed, then check the FLASH_ERASE_ERR bit to verify the
operation was successful.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..6</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">5</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_READ_ERR"></a>FLASH_READ_ERR</span><span class="attr"> </span></p>
<p>This bit is asserted when a read operation fails. Clear this error
by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the
event of a read error...
<li>the data in FLASH_READ_DATA_REG is invalid.</li>
<li>attempts to disable write protection will be ignored.</li>
<li>attempts to read/write/erase the flash will be ignored.</li></p>
</td>
</tr>
<tr valign="top">
<td class="bits">4</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_READ_IDLE"></a>FLASH_READ_IDLE</span><span class="attr"> </span></p>
<p>This bit is de-asserted when a read operation is in progress. Poll
this bit after strobing the FLASH_READ_STB bit of
FLASH_CONTROL_REG to determine when the read operation has
completed, then check the FLASH_READ_ERR bit to verify the
operation was successful.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">3..1</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_WP_ENABLED"></a>FLASH_WP_ENABLED</span><span class="attr"> </span></p>
<p>This bit is asserted when the flash is write protected and
de-asserted when write protection is disabled.
<li>Write protection must be enabled prior to performing read
operations.</li>
<li>Write protection must be disabled prior to performing write and
erase operations.</li></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RECONFIG_REGMAP|FLASH_CONTROL_REG"></a>
<h3 class="register">Offset 0x0004: FLASH_CONTROL_REG Register (W)</h3>
<a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_CONTROL_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_CONTROL_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_CONTROL_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|RECONFIG">MB_CPLD_PS_REGMAP|RECONFIG</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000040</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">FLASH_CONTROL_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0004</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000044
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>
</div>
<div class="info">
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..11</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">10w</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|CLEAR_FLASH_ERASE_ERROR_STB"></a>CLEAR_FLASH_ERASE_ERROR_STB</span><span class="attr"> (Strobe)</span></p>
<p>Strobe this bit to clear an erase error.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">9w</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|CLEAR_FLASH_WRITE_ERROR_STB"></a>CLEAR_FLASH_WRITE_ERROR_STB</span><span class="attr"> (Strobe)</span></p>
<p>Strobe this bit to clear a write error.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">8w</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|CLEAR_FLASH_READ_ERROR_STB"></a>CLEAR_FLASH_READ_ERROR_STB</span><span class="attr"> (Strobe)</span></p>
<p>Strobe this bit to clear a read error.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..5w</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_SECTOR"></a>FLASH_ERASE_SECTOR</span><span class="attr"> (Strobe)</span></p>
<p>Defines the sector to be erased. Has to be set latest with the
write access which starts the erase operation by strobing
<a href="#RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_STB">FLASH_ERASE_STB</a>.<br>
With 10M04 variants, if the flash is configured to support memory
initialization (see <a href="#RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_MEM_INIT_ENABLED">FLASH_MEM_INIT_ENABLED</a> flag) the sectors 2
to 4 have to be erased. If the flag is not asserted only sector 4
has to be erased.
With 10M08 variants, the sectors to be erased are 3 to 5 when
using memory initialization or only sector 5 otherwise.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">4w</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_STB"></a>FLASH_ERASE_STB</span><span class="attr"> (Strobe)</span></p>
<p>Strobe this bit to erase the primary Max10 configuration image
(CFM0).
<li>Prior to strobing this bit verify no other write or erase
operations are in progress, write protection is disabled, and no
error bits are asserted by reading FLASH_STATUS_REG.</li>
<li>Attempts to erase the primary image while other write or erase
operations are in progress will be ignored.
<li>Attempts to erase the primary image when write protection is
enabled will be ignored.</li>
<li>Strobing this bit and FLASH_WRITE_STB simultaneously will
result both the erase and the write operation being ignored, both
corresponding error bits being set, and write protection being
re-enabled.</li>
<li>After strobing this bit poll the FLASH_ERASE_IDLE and
FLASH_ERASE_ERR bits of FLASH_STATUS_REG to determine when
the erase operation is complete and if it was successful.</li></p>
</td>
</tr>
<tr valign="top">
<td class="bits">3w</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_WRITE_STB"></a>FLASH_WRITE_STB</span><span class="attr"> (Strobe)</span></p>
<p>Strobe this bit to write the data contained in
FLASH_WRITE_DATA_REG to the flash address identified in
FLASH_ADDR_REG.
<li>The flash must be erased before writing new data.</li>
<li>Prior to strobing this bit verify write protection is
disabled, no other write or erase operations are in progress, and
no error bits are asserted by reading FLASH_STATUS_REG.</li>
<li>Attempts to write data while other write or erase operations
are in progress will be ignored.</li>
<li>Attempts to write data with write protection enabled will be
ignored.</li>
<li>Strobing this bit and FLASH_ERASE_STB simultaneously will
result in both the write and erase operation being ignored,
both corresponding error bits being set, and write protection
being re-enabled.</li>
<li>After strobing this bit poll theMax10FlashWriteIdle and
FLASH_WRITE_ERR bits of FLASH_STATUS_REG to determine when
the write operation is complete and if it was successful.</li></p>
</td>
</tr>
<tr valign="top">
<td class="bits">2w</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_READ_STB"></a>FLASH_READ_STB</span><span class="attr"> (Strobe)</span></p>
<p>Strobe this bit to read data from the flash address identified in
FLASH_ADDR_REG.
<li>Prior to strobing this bit verify no read, write, or erase
operations are in progress, no error bits are asserted, and
write protection is enabled by reading FLASH_STATUS_REG.</li>
<li>Attempts to read data while other operations are in progress
or while write protection is disabled will be ignored.</li>
<li>After strobing this bit poll the FLASH_READ_IDLE and
FLASH_READ_ERR bits of FLASH_STATUS_REG to determine when
the read operation is complete and if it was successful.</li>
<li>Upon successful completion the data read from flash will be
available in FLASH_READ_DATA_REG.</li></p>
</td>
</tr>
<tr valign="top">
<td class="bits">1w</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_DISABLE_WP_STB"></a>FLASH_DISABLE_WP_STB</span><span class="attr"> (Strobe)</span></p>
<p>Strobe this bit to disable write protection to the section of the
Max 10 on-chip flash storing the primary configuration image
(CFM0).
<li>Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to
determine the current state of write protection.</li>
<li>Prior to strobing this bit verify no read operations are in
progress and no error bits are asserted by reading
FLASH_STATUS_REG.</li>
<li>Attempts to disable write protection while a read is in
progress will be ignored.</li>
<li>Attempts to disable write protection will be ignored if
this bit is strobed simultaneously with either FLASH_READ_STB
or FLASH_ENABLE_WP_STB.</li>
<li>Write protection must be disabled prior to performing erase or
write operations.</li>
<li>Upon completion of erase/write operations write protection
will remain disabled. When not actively erasing or writing a new
image write protection should be enabled to avoid data
corruption.</li></p>
</td>
</tr>
<tr valign="top">
<td class="bits">0w</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ENABLE_WP_STB"></a>FLASH_ENABLE_WP_STB</span><span class="attr"> (Strobe)</span></p>
<p>Strobe this bit to enable write protection to the section of the
Max 10 on-chip flash storing the primary configuration image
(CFM0).
<li>Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to
determine the current state of write protection.</li>
<li>Prior to strobing this bit verify no write or erase operations
are in progress and no error bits are asserted by reading
FLASH_STATUS_REG.</li>
<li>Attempts to enable write protection while erase or write
operations are in progress will be ignored.</li>
<li>Write protection must be enabled prior to performing
read operations.</li>
<li>Write protection should be enabled after completing
write or erase operations to prevent data corruption.</li></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RECONFIG_REGMAP|FLASH_ADDR_REG"></a>
<h3 class="register">Offset 0x0008: FLASH_ADDR_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_ADDR_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_ADDR_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_ADDR_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|RECONFIG">MB_CPLD_PS_REGMAP|RECONFIG</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000040</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">FLASH_ADDR_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0008</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000048
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>
</div>
<div class="info">
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..17</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">16..0</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_ADDR_REG|FLASH_ADDR"></a>FLASH_ADDR</span><span class="attr"> </span></p>
<p>This field holds the target address for the next read or
write operation. Set this field prior to strobing the
FLASH_WRITE_STB and FLASH_READ_STB bits of
FLASH_CONTROL_REG. Valid addresses are defined by the
FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RECONFIG_REGMAP|FLASH_WRITE_DATA_REG"></a>
<h3 class="register">Offset 0x000C: FLASH_WRITE_DATA_REG Register (W)</h3>
<a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_WRITE_DATA_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_WRITE_DATA_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_WRITE_DATA_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|RECONFIG">MB_CPLD_PS_REGMAP|RECONFIG</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000040</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">FLASH_WRITE_DATA_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x000C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x00004C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>
</div>
<div class="info">
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..0w</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_WRITE_DATA_REG|FLASH_WRITE_DATA"></a>FLASH_WRITE_DATA</span><span class="attr"> </span></p>
<p>Data in this register will be written to the flash at the address
identified in FLASH_ADDR_REG when a successful write operation
is executed.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RECONFIG_REGMAP|FLASH_READ_DATA_REG"></a>
<h3 class="register">Offset 0x0010: FLASH_READ_DATA_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_READ_DATA_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_READ_DATA_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_READ_DATA_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|RECONFIG">MB_CPLD_PS_REGMAP|RECONFIG</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000040</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">FLASH_READ_DATA_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0010</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000050
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>
</div>
<div class="info">
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..0</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_READ_DATA_REG|FLASH_READ_DATA"></a>FLASH_READ_DATA</span><span class="attr"> </span></p>
<p>This register contains data read from the flash address identified
in FLASH_ADDR_REG after a successful read operation is executed.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG"></a>
<h3 class="register">Offset 0x0014: FLASH_CFM0_START_ADDR_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|RECONFIG">MB_CPLD_PS_REGMAP|RECONFIG</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000040</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">FLASH_CFM0_START_ADDR_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0014</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000054
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>
</div>
<div class="info">
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..0</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG|FLASH_CFM0_START_ADDR"></a>FLASH_CFM0_START_ADDR</span><span class="attr"> </span></p>
<p>Start address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM).</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG"></a>
<h3 class="register">Offset 0x0018: FLASH_CFM0_END_ADDR_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG_in')">(<span id="show_RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_SPI1_CS3">ARM_SPI1_CS3</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#MB_CPLD_PS_REGMAP|RECONFIG">MB_CPLD_PS_REGMAP|RECONFIG</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000040</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">FLASH_CFM0_END_ADDR_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0018</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x000058
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file reconfig_engine.v.</p>
</div>
<div class="info">
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..0</td>
<td>
<p><span class="name"><a name="RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG|FLASH_CFM0_END_ADDR"></a>FLASH_CFM0_END_ADDR</span><span class="attr"> </span></p>
<p>Last address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM).</p>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="regmap">
<a name="RFDC_REGS_REGMAP"></a>
<h1 class="regmap">RFDC_REGS_REGMAP</h1>
<div class="group"><a name="RFDC_REGS_REGMAP|RFDC_REGS"></a><h2 class="group">RFDC_REGS</h2>
These are the registers located within the RFDC block design
that provide control and status support for the RF chain.
<div class="enum">
<a name="RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM"></a>
<h3 class="enum">FABRIC_DSP_BW_ENUM Enumeration</h3>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' colspan='2'> Value </td>
<td class="l" rowspan='2' colspan='1'> Name </td>
</tr>
<tr class="header2" valign="bottom">
<td class='value'> Dec </td>
<td class='l'> Hex </td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM|FABRIC_DSP_BW_NONE'></a>FABRIC_DSP_BW_NONE</p>
</td>
</tr>
<tr valign="top">
<td class='value'>100</td>
<td class='l'>0x064</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM|FABRIC_DSP_BW_100M'></a>FABRIC_DSP_BW_100M</p>
</td>
</tr>
<tr valign="top">
<td class='value'>200</td>
<td class='l'>0x0C8</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM|FABRIC_DSP_BW_200M'></a>FABRIC_DSP_BW_200M</p>
</td>
</tr>
<tr valign="top">
<td class='value'>400</td>
<td class='l'>0x190</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM|FABRIC_DSP_BW_400M'></a>FABRIC_DSP_BW_400M</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file common_regs.v.
</p>
</div>
<div class="register">
<a name="RFDC_REGS_REGMAP|MMCM"></a>
<h3 class="register">Offset 0x0000: MMCM Window (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_REGS_REGMAP|MMCM_in')">(<span id="show_RFDC_REGS_REGMAP|MMCM_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_REGS_REGMAP|MMCM_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|RFDC_REGS">AXI_HPM0_REGMAP|RFDC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000140000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">MMCM</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
<tr><td class="offset_info" align="right"> size=0x10000 (64 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000140000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
Register space for controlling the data clock MMCM instance
within the RFDC block design.
Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the
regiter space description in chapter 2.
(https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)
</div>
</div>
<div class="register">
<a name="RFDC_REGS_REGMAP|INVERT_IQ_REG"></a>
<h3 class="register">Offset 0x10000: INVERT_IQ_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_REGS_REGMAP|INVERT_IQ_REG_in')">(<span id="show_RFDC_REGS_REGMAP|INVERT_IQ_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_REGS_REGMAP|INVERT_IQ_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|RFDC_REGS">AXI_HPM0_REGMAP|RFDC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000140000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">INVERT_IQ_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x10000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000150000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
Control register for inverting I/Q data.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB1_DAC3_IQ"></a>INVERT_DB1_DAC3_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">14</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB1_DAC2_IQ"></a>INVERT_DB1_DAC2_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">13</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB1_DAC1_IQ"></a>INVERT_DB1_DAC1_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">12</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB1_DAC0_IQ"></a>INVERT_DB1_DAC0_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB0_DAC3_IQ"></a>INVERT_DB0_DAC3_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">10</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB0_DAC2_IQ"></a>INVERT_DB0_DAC2_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">9</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB0_DAC1_IQ"></a>INVERT_DB0_DAC1_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">8</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB0_DAC0_IQ"></a>INVERT_DB0_DAC0_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB1_ADC3_IQ"></a>INVERT_DB1_ADC3_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">6</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB1_ADC2_IQ"></a>INVERT_DB1_ADC2_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">5</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB1_ADC1_IQ"></a>INVERT_DB1_ADC1_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">4</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB1_ADC0_IQ"></a>INVERT_DB1_ADC0_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">3</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB0_ADC3_IQ"></a>INVERT_DB0_ADC3_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">2</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB0_ADC2_IQ"></a>INVERT_DB0_ADC2_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">1</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB0_ADC1_IQ"></a>INVERT_DB0_ADC1_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|INVERT_IQ_REG|INVERT_DB0_ADC0_IQ"></a>INVERT_DB0_ADC0_IQ</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RFDC_REGS_REGMAP|MMCM_RESET_REG"></a>
<h3 class="register">Offset 0x11000: MMCM_RESET_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_REGS_REGMAP|MMCM_RESET_REG_in')">(<span id="show_RFDC_REGS_REGMAP|MMCM_RESET_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_REGS_REGMAP|MMCM_RESET_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|RFDC_REGS">AXI_HPM0_REGMAP|RFDC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000140000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">MMCM_RESET_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x11000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000151000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
Control register for resetting the data clock MMCM.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..1</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|MMCM_RESET_REG|RESET_MMCM"></a>RESET_MMCM</span><span class="attr"> </span></p>
<p>Write a '1' to this bit to reset the MMCM. Then write a
'0' to place the MMCM out of reset.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG"></a>
<h3 class="register">Offset 0x12000: RF_RESET_CONTROL_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG_in')">(<span id="show_RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|RFDC_REGS">AXI_HPM0_REGMAP|RFDC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000140000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RF_RESET_CONTROL_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x12000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000152000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
Control register for the RF reset controller.
Verify the FSM ID before polling starting any reset sequence.
To use the SW reset triggers: Wait until DB*_DONE is de-asserted.
Assert either the *_RESET or *_ENABLE bitfields.
Wait until DB*_DONE is asserted to release the trigger.
The DB*_DONE signal should then de-assert.<BR/>
<b>Note: The *_DB1 constants are not used in the HDL, their purpose is
merely for documentation.</b>
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..10</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">9</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG|DAC_ENABLE"></a>DAC_ENABLE</span><span class="attr"> </span></p>
<p>Write a '1' to this bit to trigger the enable sequence for
the daughterboard 0 DAC chain. Write a '0' once
db0_dac_seq_done is asserted.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">8</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG|DAC_RESET"></a>DAC_RESET</span><span class="attr"> </span></p>
<p>Write a '1' to this bit to trigger a reset for the
daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done
is asserted.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..6</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">5</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG|ADC_ENABLE"></a>ADC_ENABLE</span><span class="attr"> </span></p>
<p>Write a '1' to this bit to trigger the enable sequence for
the daughterboard 0 ADC chain. Write a '0' once
db0_adc_seq_done is asserted.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">4</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG|ADC_RESET"></a>ADC_RESET</span><span class="attr"> </span></p>
<p>Write a '1' to this bit to trigger a reset for the
daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done
is asserted.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">3..1</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG|FSM_RESET"></a>FSM_RESET</span><span class="attr"> </span></p>
<p>Write a '1' to this bit to reset the RF reset controller.
Write a '0' once db0_fsm_reset_done asserts.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RFDC_REGS_REGMAP|RF_RESET_STATUS_REG"></a>
<h3 class="register">Offset 0x12008: RF_RESET_STATUS_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_REGS_REGMAP|RF_RESET_STATUS_REG_in')">(<span id="show_RFDC_REGS_REGMAP|RF_RESET_STATUS_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_REGS_REGMAP|RF_RESET_STATUS_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|RFDC_REGS">AXI_HPM0_REGMAP|RFDC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000140000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RF_RESET_STATUS_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x12008</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000152008
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
Status register for the RF reset controller.
Verify the FSM ID before polling starting any reset sequence.
Refer to RF_RESET_CONTROL_REG for instructions on how to use
the status bits in this register.<BR/>
<b>Note: The *_DB1 constants are not used in the HDL, their purpose is
merely for documentation.</b>
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_RESET_STATUS_REG|DAC_SEQ_DONE"></a>DAC_SEQ_DONE</span><span class="attr"> </span></p>
<p>This bit asserts ('1') when the DB0 DAC chain reset sequence
is completed. The bitfield deasserts ('0') after
deasserting the issued triggered (enable or reset).</p>
</td>
</tr>
<tr valign="top">
<td class="bits">10..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_RESET_STATUS_REG|ADC_SEQ_DONE"></a>ADC_SEQ_DONE</span><span class="attr"> </span></p>
<p>This bit asserts ('1') when the DB0 ADC chain reset sequence
is completed. The bitfield deasserts ('0') after
deasserting the issued triggered (enable or reset).</p>
</td>
</tr>
<tr valign="top">
<td class="bits">6..4</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">3</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_RESET_STATUS_REG|FSM_RESET_DONE"></a>FSM_RESET_DONE</span><span class="attr"> </span></p>
<p>This bit asserts ('1') when the DB0 RF reset controller FSM
reset sequence is completed. The bitfield deasserts ('0')
after deasserting db0_fsm_reset.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">2..0</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG"></a>
<h3 class="register">Offset 0x13000: RF_AXI_STATUS_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_REGS_REGMAP|RF_AXI_STATUS_REG_in')">(<span id="show_RFDC_REGS_REGMAP|RF_AXI_STATUS_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_REGS_REGMAP|RF_AXI_STATUS_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|RFDC_REGS">AXI_HPM0_REGMAP|RFDC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000140000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RF_AXI_STATUS_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x13000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000153000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
Status register for the RF AXI-Stream interfaces.<BR/>
<b>Note: The *_DB1 constants are not used in the HDL, their purpose is
merely for documentation.</b>
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..30</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|USER_ADC_TREADY_DB1"></a>USER_ADC_TREADY_DB1</span><span class="attr"> </span></p>
<p>This bitfield is wired to the user's ADC (DB1) AXI-Stream
TReady handshake signals. The LSB is channel 0 and the MSB
is channel 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">29..28</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|USER_ADC_TVALID_DB1"></a>USER_ADC_TVALID_DB1</span><span class="attr"> </span></p>
<p>This bitfield is wired to the user's ADC (DB1) AXI-Stream
TValid handshake signals. The LSB is channel 0 and the MSB
is channel 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..26</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|RFDC_ADC_I_TVALID_DB1"></a>RFDC_ADC_I_TVALID_DB1</span><span class="attr"> </span></p>
<p>This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
TValid handshake signals (I portion). The LSB is channel 0
and the MSB is channel 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">25..24</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|RFDC_ADC_Q_TVALID_DB1"></a>RFDC_ADC_Q_TVALID_DB1</span><span class="attr"> </span></p>
<p>This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
TValid handshake signals (Q portion). The LSB is channel 0
and the MSB is channel 1.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..22</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|RFDC_ADC_I_TREADY_DB1"></a>RFDC_ADC_I_TREADY_DB1</span><span class="attr"> </span></p>
<p>This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
TReady handshake signals (I portion). The LSB is channel 0
and the MSB is channel 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">21..20</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|RFDC_ADC_Q_TREADY_DB1"></a>RFDC_ADC_Q_TREADY_DB1</span><span class="attr"> </span></p>
<p>This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
TReady handshake signals (Q portion). The LSB is channel 0
and the MSB is channel 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">19..18</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|RFDC_DAC_TVALID_DB1"></a>RFDC_DAC_TVALID_DB1</span><span class="attr"> </span></p>
<p>This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
TValid handshake signals. The LSB is channel 0 and the MSB
is channel 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">17..16</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|RFDC_DAC_TREADY_DB1"></a>RFDC_DAC_TREADY_DB1</span><span class="attr"> </span></p>
<p>This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
TReady handshake signals. The LSB is channel 0 and the MSB
is channel 1.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..14</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|USER_ADC_TREADY"></a>USER_ADC_TREADY</span><span class="attr"> </span></p>
<p>This bitfield is wired to the user's ADC (DB0) AXI-Stream
TReady handshake signals. The LSB is channel 0 and the MSB
is channel 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">13..12</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|USER_ADC_TVALID"></a>USER_ADC_TVALID</span><span class="attr"> </span></p>
<p>This bitfield is wired to the user's ADC (DB0) AXI-Stream
TValid handshake signals. The LSB is channel 0 and the MSB
is channel 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..10</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|RFDC_ADC_I_TVALID"></a>RFDC_ADC_I_TVALID</span><span class="attr"> </span></p>
<p>This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
TValid handshake signals (I portion). The LSB is channel 0
and the MSB is channel 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">9..8</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|RFDC_ADC_Q_TVALID"></a>RFDC_ADC_Q_TVALID</span><span class="attr"> </span></p>
<p>This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
TValid handshake signals (Q portion). The LSB is channel 0
and the MSB is channel 1.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..6</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|RFDC_ADC_I_TREADY"></a>RFDC_ADC_I_TREADY</span><span class="attr"> </span></p>
<p>This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
TReady handshake signals (I portion). The LSB is channel 0
and the MSB is channel 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">5..4</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|RFDC_ADC_Q_TREADY"></a>RFDC_ADC_Q_TREADY</span><span class="attr"> </span></p>
<p>This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
TReady handshake signals (Q portion). The LSB is channel 0
and the MSB is channel 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">3..2</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|RFDC_DAC_TVALID"></a>RFDC_DAC_TVALID</span><span class="attr"> </span></p>
<p>This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
TValid handshake signals. The LSB is channel 0 and the MSB
is channel 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">1..0</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_AXI_STATUS_REG|RFDC_DAC_TREADY"></a>RFDC_DAC_TREADY</span><span class="attr"> </span></p>
<p>This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
TReady handshake signals. The LSB is channel 0 and the MSB
is channel 1.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RFDC_REGS_REGMAP|FABRIC_DSP_REG"></a>
<h3 class="register">Offset 0x13008: FABRIC_DSP_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_REGS_REGMAP|FABRIC_DSP_REG_in')">(<span id="show_RFDC_REGS_REGMAP|FABRIC_DSP_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_REGS_REGMAP|FABRIC_DSP_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|RFDC_REGS">AXI_HPM0_REGMAP|RFDC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000140000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">FABRIC_DSP_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x13008</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000153008
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
This register provides information to the driver on the type
of DSP that is instantiated in the fabric.<BR/>
The X410 platform supports multiple RF daughterboards, each requiring
a different fabric RF DSP chain that works with specific RFDC settings.
Each bandwidth DSP chain has a unique identifier (BW in MHz), this
information is conveyed in this register to let the driver
configure the RFDC with the proper settings.
Also, channel count for the DSP module is included.<BR/>
<b>Note: The *_DB1 constants are not used in the HDL, their purpose is
merely for documentation.</b>
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..30</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|FABRIC_DSP_REG|FABRIC_DSP_TX_CNT_DB1"></a>FABRIC_DSP_TX_CNT_DB1</span><span class="attr"> (initialvalue=0)</span></p>
<p>Fabric DSP TX channel count for daughterboard 0.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">29..28</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|FABRIC_DSP_REG|FABRIC_DSP_RX_CNT_DB1"></a>FABRIC_DSP_RX_CNT_DB1</span><span class="attr"> (initialvalue=0)</span></p>
<p>Fabric DSP RX channel count for daughterboard 0.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..16</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|FABRIC_DSP_REG|FABRIC_DSP_BW_DB1"></a>FABRIC_DSP_BW_DB1</span><span class="attr"> (initialvalue=FABRIC_DSP_BW_NONE)</span></p>
<p>Fabric DSP BW in MHz for daughterboard 1.</p>
<p>
The values for this bitfield are in the <a href="#RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM">FABRIC_DSP_BW_ENUM</a> table.
<a class="sh_enum" href="javascript:sb('RFDC_REGS_REGMAP|FABRIC_DSP_REG|FABRIC_DSP_BW_DB1')">(<span id="show_RFDC_REGS_REGMAP|FABRIC_DSP_REG|FABRIC_DSP_BW_DB1">show here</span>)</a>
</p>
<div class="sh_enum" id="div_RFDC_REGS_REGMAP|FABRIC_DSP_REG|FABRIC_DSP_BW_DB1">
<div class="enum">
<a name="RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM"></a>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' colspan='2'> Value </td>
<td class="l" rowspan='2' colspan='1'> Name </td>
</tr>
<tr class="header2" valign="bottom">
<td class='value'> Dec </td>
<td class='l'> Hex </td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM|FABRIC_DSP_BW_NONE'></a>FABRIC_DSP_BW_NONE</p>
</td>
</tr>
<tr valign="top">
<td class='value'>100</td>
<td class='l'>0x064</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM|FABRIC_DSP_BW_100M'></a>FABRIC_DSP_BW_100M</p>
</td>
</tr>
<tr valign="top">
<td class='value'>200</td>
<td class='l'>0x0C8</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM|FABRIC_DSP_BW_200M'></a>FABRIC_DSP_BW_200M</p>
</td>
</tr>
<tr valign="top">
<td class='value'>400</td>
<td class='l'>0x190</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM|FABRIC_DSP_BW_400M'></a>FABRIC_DSP_BW_400M</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file common_regs.v.
</p>
</div>
</div>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..14</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|FABRIC_DSP_REG|FABRIC_DSP_TX_CNT"></a>FABRIC_DSP_TX_CNT</span><span class="attr"> (initialvalue=0)</span></p>
<p>Fabric DSP TX channel count for daughterboard 0.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">13..12</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|FABRIC_DSP_REG|FABRIC_DSP_RX_CNT"></a>FABRIC_DSP_RX_CNT</span><span class="attr"> (initialvalue=0)</span></p>
<p>Fabric DSP RX channel count for daughterboard 0.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|FABRIC_DSP_REG|FABRIC_DSP_BW"></a>FABRIC_DSP_BW</span><span class="attr"> (initialvalue=FABRIC_DSP_BW_NONE)</span></p>
<p>Fabric DSP BW in MHz for daughterboard 0.</p>
<p>
The values for this bitfield are in the <a href="#RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM">FABRIC_DSP_BW_ENUM</a> table.
<a class="sh_enum" href="javascript:sb('RFDC_REGS_REGMAP|FABRIC_DSP_REG|FABRIC_DSP_BW')">(<span id="show_RFDC_REGS_REGMAP|FABRIC_DSP_REG|FABRIC_DSP_BW">show here</span>)</a>
</p>
<div class="sh_enum" id="div_RFDC_REGS_REGMAP|FABRIC_DSP_REG|FABRIC_DSP_BW">
<div class="enum">
<a name="RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM"></a>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' colspan='2'> Value </td>
<td class="l" rowspan='2' colspan='1'> Name </td>
</tr>
<tr class="header2" valign="bottom">
<td class='value'> Dec </td>
<td class='l'> Hex </td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM|FABRIC_DSP_BW_NONE'></a>FABRIC_DSP_BW_NONE</p>
</td>
</tr>
<tr valign="top">
<td class='value'>100</td>
<td class='l'>0x064</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM|FABRIC_DSP_BW_100M'></a>FABRIC_DSP_BW_100M</p>
</td>
</tr>
<tr valign="top">
<td class='value'>200</td>
<td class='l'>0x0C8</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM|FABRIC_DSP_BW_200M'></a>FABRIC_DSP_BW_200M</p>
</td>
</tr>
<tr valign="top">
<td class='value'>400</td>
<td class='l'>0x190</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM|FABRIC_DSP_BW_400M'></a>FABRIC_DSP_BW_400M</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file common_regs.v.
</p>
</div>
</div>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RFDC_REGS_REGMAP|CALIBRATION_DATA"></a>
<h3 class="register">Offset 0x14000: CALIBRATION_DATA Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_REGS_REGMAP|CALIBRATION_DATA_in')">(<span id="show_RFDC_REGS_REGMAP|CALIBRATION_DATA_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_REGS_REGMAP|CALIBRATION_DATA_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|RFDC_REGS">AXI_HPM0_REGMAP|RFDC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000140000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CALIBRATION_DATA</td></tr>
<tr><td class="offset_info" align="right"> offset=0x14000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000154000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
The fields of this register provide data to all the DAC channels when enabled
by the CALIBRATION_ENABLE register.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..16</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|CALIBRATION_DATA|Q_DATA"></a>Q_DATA</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..0</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|CALIBRATION_DATA|I_DATA"></a>I_DATA</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RFDC_REGS_REGMAP|CALIBRATION_ENABLE"></a>
<h3 class="register">Offset 0x14008: CALIBRATION_ENABLE Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_REGS_REGMAP|CALIBRATION_ENABLE_in')">(<span id="show_RFDC_REGS_REGMAP|CALIBRATION_ENABLE_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_REGS_REGMAP|CALIBRATION_ENABLE_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|RFDC_REGS">AXI_HPM0_REGMAP|RFDC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000140000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CALIBRATION_ENABLE</td></tr>
<tr><td class="offset_info" align="right"> offset=0x14008</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000154008
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
This register enables calibration data in the DAC data path for each of the
four channels. Each of these bits is normally '0'. When written '1', DAC data
for the corresponding channel will be constantly driven with the contents of
the CALIBRATION_DATA register.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..6</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">5</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|CALIBRATION_ENABLE|ENABLE_CALIBRATION_DATA_3"></a>ENABLE_CALIBRATION_DATA_3</span><span class="attr"> </span></p>
<p>Enables calibration data for channel 3.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">4</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|CALIBRATION_ENABLE|ENABLE_CALIBRATION_DATA_2"></a>ENABLE_CALIBRATION_DATA_2</span><span class="attr"> </span></p>
<p>Enables calibration data for channel 2.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">3..2</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">1</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|CALIBRATION_ENABLE|ENABLE_CALIBRATION_DATA_1"></a>ENABLE_CALIBRATION_DATA_1</span><span class="attr"> </span></p>
<p>Enables calibration data for channel 1.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|CALIBRATION_ENABLE|ENABLE_CALIBRATION_DATA_0"></a>ENABLE_CALIBRATION_DATA_0</span><span class="attr"> </span></p>
<p>Enables calibration data for channel 0.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RFDC_REGS_REGMAP|THRESHOLD_STATUS"></a>
<h3 class="register">Offset 0x15000: THRESHOLD_STATUS Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_REGS_REGMAP|THRESHOLD_STATUS_in')">(<span id="show_RFDC_REGS_REGMAP|THRESHOLD_STATUS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_REGS_REGMAP|THRESHOLD_STATUS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|RFDC_REGS">AXI_HPM0_REGMAP|RFDC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000140000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">THRESHOLD_STATUS</td></tr>
<tr><td class="offset_info" align="right"> offset=0x15000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000155000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
This register shows threshold status for the ADCs. Each bit reflects the
RFDC's real-time ADC status signals, which will assert when the ADC input
signal exceeds the programmed threshold value. The status will remain
asserted until cleared by software.
The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is
the location of the tile in the converter column and ZZ is either 01 (the
lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
See also the Xilinx document PG269.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..12</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|THRESHOLD_STATUS|ADC2_23_THRESHOLD2"></a>ADC2_23_THRESHOLD2</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">10</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|THRESHOLD_STATUS|ADC2_23_THRESHOLD1"></a>ADC2_23_THRESHOLD1</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">9</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|THRESHOLD_STATUS|ADC2_01_THRESHOLD2"></a>ADC2_01_THRESHOLD2</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">8</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|THRESHOLD_STATUS|ADC2_01_THRESHOLD1"></a>ADC2_01_THRESHOLD1</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..4</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">3</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|THRESHOLD_STATUS|ADC0_23_THRESHOLD2"></a>ADC0_23_THRESHOLD2</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">2</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|THRESHOLD_STATUS|ADC0_23_THRESHOLD1"></a>ADC0_23_THRESHOLD1</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">1</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|THRESHOLD_STATUS|ADC0_01_THRESHOLD2"></a>ADC0_01_THRESHOLD2</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|THRESHOLD_STATUS|ADC0_01_THRESHOLD1"></a>ADC0_01_THRESHOLD1</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG"></a>
<h3 class="register">Offset 0x16000: RF_PLL_CONTROL_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG_in')">(<span id="show_RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|RFDC_REGS">AXI_HPM0_REGMAP|RFDC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000140000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RF_PLL_CONTROL_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x16000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000156000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
Enable RF MMCM outputs.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..17</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">16</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG|CLEAR_DATA_CLK_UNLOCKED"></a>CLEAR_DATA_CLK_UNLOCKED</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..13</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">12</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG|ENABLE_RF_CLK_2X"></a>ENABLE_RF_CLK_2X</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..9</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">8</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG|ENABLE_RF_CLK"></a>ENABLE_RF_CLK</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..5</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">4</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG|ENABLE_DATA_CLK_2X"></a>ENABLE_DATA_CLK_2X</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">3..1</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">0</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG|ENABLE_DATA_CLK"></a>ENABLE_DATA_CLK</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RFDC_REGS_REGMAP|RF_PLL_STATUS_REG"></a>
<h3 class="register">Offset 0x16008: RF_PLL_STATUS_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_REGS_REGMAP|RF_PLL_STATUS_REG_in')">(<span id="show_RFDC_REGS_REGMAP|RF_PLL_STATUS_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_REGS_REGMAP|RF_PLL_STATUS_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|RFDC_REGS">AXI_HPM0_REGMAP|RFDC_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1000140000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RF_PLL_STATUS_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x16008</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x1000156008
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file common_regs.v.</p>
</div>
<div class="info">
Data Clk Pll Status Register
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..21</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">20</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_PLL_STATUS_REG|DATA_CLK_PLL_LOCKED"></a>DATA_CLK_PLL_LOCKED</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">19..17</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">16</td>
<td>
<p><span class="name"><a name="RFDC_REGS_REGMAP|RF_PLL_STATUS_REG|DATA_CLK_PLL_UNLOCKED_STICKY"></a>DATA_CLK_PLL_UNLOCKED_STICKY</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..0</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="regmap">
<a name="RFDC_TIMING_REGMAP"></a>
<h1 class="regmap">RFDC_TIMING_REGMAP</h1>
<div class="group"><a name="RFDC_TIMING_REGMAP|RFDC_TIMING_REGS"></a><h2 class="group">RFDC_TIMING_REGS</h2>
<div class="register">
<a name="RFDC_TIMING_REGMAP|NCO_RESET_REG"></a>
<h3 class="register">Offset 0x0000: NCO_RESET_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_TIMING_REGMAP|NCO_RESET_REG_in')">(<span id="show_RFDC_TIMING_REGMAP|NCO_RESET_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_TIMING_REGMAP|NCO_RESET_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW">RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">NCO_RESET_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x008000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file rfdc_timing_control.v.</p>
</div>
<div class="info">
NCO reset control register.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..2</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">1r</td>
<td>
<p><span class="name"><a name="RFDC_TIMING_REGMAP|NCO_RESET_REG|NCO_RESET_DONE"></a>NCO_RESET_DONE</span><span class="attr"> </span></p>
<p>When 1, indicates that the NCO reset has completed.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">0w</td>
<td>
<p><span class="name"><a name="RFDC_TIMING_REGMAP|NCO_RESET_REG|NCO_RESET_START"></a>NCO_RESET_START</span><span class="attr"> (Strobe)</span></p>
<p>Write a 1 to this bit to start a reset the RFDC's NCO.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="RFDC_TIMING_REGMAP|GEARBOX_RESET_REG"></a>
<h3 class="register">Offset 0x0004: GEARBOX_RESET_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('RFDC_TIMING_REGMAP|GEARBOX_RESET_REG_in')">(<span id="show_RFDC_TIMING_REGMAP|GEARBOX_RESET_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RFDC_TIMING_REGMAP|GEARBOX_RESET_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW">RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right"> 0x008000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">GEARBOX_RESET_REG</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0004</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x008004
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file rfdc_timing_control.v.</p>
</div>
<div class="info">
Gearbox reset control register.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..2</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">1w</td>
<td>
<p><span class="name"><a name="RFDC_TIMING_REGMAP|GEARBOX_RESET_REG|DAC_RESET"></a>DAC_RESET</span><span class="attr"> (Strobe)</span></p>
<p>This reset is for the gearbox on the DAC data path that is used to
move data from one clock domain to another outside the RFDC. Write
a 1 to this bit to send a reset pulse to the DAC gearbox.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">0w</td>
<td>
<p><span class="name"><a name="RFDC_TIMING_REGMAP|GEARBOX_RESET_REG|ADC_RESET"></a>ADC_RESET</span><span class="attr"> (Strobe)</span></p>
<p>This reset is for the gearbox on the ADC data path that is used to
move data from one clock domain to another outside the RFDC. Write
a 1 to this bit to send a reset pulse to the ADC gearbox.</p>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="regmap">
<a name="SPI_REGMAP"></a>
<h1 class="regmap">SPI_REGMAP</h1>
<div class="xmlpmd">
</div>
<div class="group"><a name="SPI_REGMAP|SPI_REGS"></a><h2 class="group">SPI_REGS</h2>
<div class="xmlpmd">
<p>This register map is present for each SPI master.</p>
<p>For information about the register content and the way to interact with the core see the
<a href="https://opencores.org/websvn/filedetails?repname=spi&path=%2Fspi%2Ftrunk%2Fdoc%2Fspi.pdf" target="_blank">documentation</a>
of the SPI master from opencores used internally.</p>
<p>The core is configured to operate with 16 slave signal signals, up to 128 bits per transmission and 8 bit clock divider.
Only 64 bits of data are available via this register interface.</p>
<p>For the different SPI modes use the following table to derive the bits in <a href="#SPI_REGMAP|CONTROL">CONTROL</a> register. Only option 0 (CPOL=0, CPHA=0) has been tested.</p>
<table>
<thead>
<tr>
<th>CPOL</th>
<th>CPHA</th>
<th>TX_NEG</th>
<th>RX_NEG</th>
</tr>
</thead>
<tbody>
<tr>
<td>0</td>
<td>0</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
</tbody>
</table></div>
<div class="register">
<a name="SPI_REGMAP|RX_DATA_LOW"></a>
<h3 class="register">Offset 0x0000: RX_DATA_LOW Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('SPI_REGMAP|RX_DATA_LOW_in')">(<span id="show_SPI_REGMAP|RX_DATA_LOW_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_SPI_REGMAP|RX_DATA_LOW_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RX_DATA_LOW</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ctrlport_to_spi.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Lower 32 bits of the received word. (RxWord[31:0])</p></div>
</div>
</div>
<div class="register">
<a name="SPI_REGMAP|RX_DATA_HIGH"></a>
<h3 class="register">Offset 0x0004: RX_DATA_HIGH Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('SPI_REGMAP|RX_DATA_HIGH_in')">(<span id="show_SPI_REGMAP|RX_DATA_HIGH_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_SPI_REGMAP|RX_DATA_HIGH_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RX_DATA_HIGH</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0004</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ctrlport_to_spi.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Higher 32 bits of the received word. (RxWord[63:32])</p></div>
</div>
</div>
<div class="register">
<a name="SPI_REGMAP|TX_DATA_LOW"></a>
<h3 class="register">Offset 0x0008: TX_DATA_LOW Register (W)</h3>
<a class="sh_addrs" href="javascript:sa('SPI_REGMAP|TX_DATA_LOW_in')">(<span id="show_SPI_REGMAP|TX_DATA_LOW_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_SPI_REGMAP|TX_DATA_LOW_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">TX_DATA_LOW</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0008</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ctrlport_to_spi.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Lower 32 bits of the received word. (TxWord[31:0])</p></div>
</div>
</div>
<div class="register">
<a name="SPI_REGMAP|TX_DATA_HIGH"></a>
<h3 class="register">Offset 0x000C: TX_DATA_HIGH Register (W)</h3>
<a class="sh_addrs" href="javascript:sa('SPI_REGMAP|TX_DATA_HIGH_in')">(<span id="show_SPI_REGMAP|TX_DATA_HIGH_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_SPI_REGMAP|TX_DATA_HIGH_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">TX_DATA_HIGH</td></tr>
<tr><td class="offset_info" align="right"> offset=0x000C</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ctrlport_to_spi.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Higher 32 bits of the received word. (TxWord[63:32])</p></div>
</div>
</div>
<div class="register">
<a name="SPI_REGMAP|CONTROL"></a>
<h3 class="register">Offset 0x0010: CONTROL Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('SPI_REGMAP|CONTROL_in')">(<span id="show_SPI_REGMAP|CONTROL_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_SPI_REGMAP|CONTROL_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CONTROL</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0010</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ctrlport_to_spi.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Control register</p></div>
</div>
</div>
<div class="register">
<a name="SPI_REGMAP|CLOCK_DIVIDER"></a>
<h3 class="register">Offset 0x0014: CLOCK_DIVIDER Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('SPI_REGMAP|CLOCK_DIVIDER_in')">(<span id="show_SPI_REGMAP|CLOCK_DIVIDER_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_SPI_REGMAP|CLOCK_DIVIDER_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CLOCK_DIVIDER</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0014</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ctrlport_to_spi.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">7..0</td>
<td>
<p><span class="name"><a name="SPI_REGMAP|CLOCK_DIVIDER|Divider"></a>Divider</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>Clock Divider.</p></div></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="SPI_REGMAP|SLAVE_SELECT"></a>
<h3 class="register">Offset 0x0018: SLAVE_SELECT Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('SPI_REGMAP|SLAVE_SELECT_in')">(<span id="show_SPI_REGMAP|SLAVE_SELECT_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_SPI_REGMAP|SLAVE_SELECT_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SLAVE_SELECT</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0018</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file ctrlport_to_spi.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">15..0</td>
<td>
<p><span class="name"><a name="SPI_REGMAP|SLAVE_SELECT|SS"></a>SS</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>Slave select.</p></div></p>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="regmap">
<a name="UIO_REGMAP"></a>
<h1 class="regmap">UIO_REGMAP</h1>
<div class="xmlpmd">
</div>
<div class="group"><a name="UIO_REGMAP|UIO_REGS"></a><h2 class="group">UIO_REGS</h2>
<div class="xmlpmd">
<p>UIO</p></div>
<div class="register">
<a name="UIO_REGMAP|IP"></a>
<h3 class="register">Offset 0x0000: IP Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('UIO_REGMAP|IP_in')">(<span id="show_UIO_REGMAP|IP_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_UIO_REGMAP|IP_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|UIO">QSFP_REGMAP|UIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00A000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">IP</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006A000
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007A000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Set this port's IP address</p></div>
</div>
</div>
<div class="register">
<a name="UIO_REGMAP|UDP"></a>
<h3 class="register">Offset 0x0004: UDP Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('UIO_REGMAP|UDP_in')">(<span id="show_UIO_REGMAP|UDP_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_UIO_REGMAP|UDP_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|UIO">QSFP_REGMAP|UIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00A000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">UDP</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0004</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000A004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001A004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002A004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003A004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004A004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005A004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006A004
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007A004
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Set the UDP port for CHDR_traffic</p></div>
</div>
</div>
<div class="register">
<a name="UIO_REGMAP|BRIDGE_MAC_LSB"></a>
<h3 class="register">Offset 0x0010: BRIDGE_MAC_LSB Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('UIO_REGMAP|BRIDGE_MAC_LSB_in')">(<span id="show_UIO_REGMAP|BRIDGE_MAC_LSB_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_UIO_REGMAP|BRIDGE_MAC_LSB_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|UIO">QSFP_REGMAP|UIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00A000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">BRIDGE_MAC_LSB</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0010</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000A010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001A010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002A010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003A010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004A010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005A010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006A010
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007A010
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>If BRIDGE_ENABLE is set use this MAC_ID</p></div>
</div>
</div>
<div class="register">
<a name="UIO_REGMAP|BRIDGE_MAC_MSB"></a>
<h3 class="register">Offset 0x0014: BRIDGE_MAC_MSB Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('UIO_REGMAP|BRIDGE_MAC_MSB_in')">(<span id="show_UIO_REGMAP|BRIDGE_MAC_MSB_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_UIO_REGMAP|BRIDGE_MAC_MSB_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|UIO">QSFP_REGMAP|UIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00A000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">BRIDGE_MAC_MSB</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0014</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000A014
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001A014
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002A014
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003A014
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004A014
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005A014
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006A014
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007A014
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>If BRIDGE_ENABLE is set use this MAC_ID</p></div>
</div>
</div>
<div class="register">
<a name="UIO_REGMAP|BRIDGE_IP"></a>
<h3 class="register">Offset 0x0018: BRIDGE_IP Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('UIO_REGMAP|BRIDGE_IP_in')">(<span id="show_UIO_REGMAP|BRIDGE_IP_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_UIO_REGMAP|BRIDGE_IP_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|UIO">QSFP_REGMAP|UIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00A000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">BRIDGE_IP</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0018</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000A018
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001A018
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002A018
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003A018
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004A018
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005A018
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006A018
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007A018
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>If BRIDGE_ENABLE is set use this IP Address</p></div>
</div>
</div>
<div class="register">
<a name="UIO_REGMAP|BRIDGE_UDP"></a>
<h3 class="register">Offset 0x001C: BRIDGE_UDP Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('UIO_REGMAP|BRIDGE_UDP_in')">(<span id="show_UIO_REGMAP|BRIDGE_UDP_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_UIO_REGMAP|BRIDGE_UDP_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|UIO">QSFP_REGMAP|UIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00A000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">BRIDGE_UDP</td></tr>
<tr><td class="offset_info" align="right"> offset=0x001C</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000A01C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001A01C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002A01C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003A01C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004A01C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005A01C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006A01C
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007A01C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>If BRIDGE_ENABLE is set use this UDP Port for CHDR_traffic</p></div>
</div>
</div>
<div class="register">
<a name="UIO_REGMAP|BRIDGE_ENABLE"></a>
<h3 class="register">Offset 0x0020: BRIDGE_ENABLE Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('UIO_REGMAP|BRIDGE_ENABLE_in')">(<span id="show_UIO_REGMAP|BRIDGE_ENABLE_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_UIO_REGMAP|BRIDGE_ENABLE_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|UIO">QSFP_REGMAP|UIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00A000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">BRIDGE_ENABLE</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0020</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000A020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001A020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002A020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003A020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004A020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005A020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006A020
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007A020
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Bit 0 Controls the following logic</p>
<pre><code class="language-verilog">always_comb begin : bridge_mux
my_mac = bridge_en ? bridge_mac_reg : mac_reg;
my_ip = bridge_en ? bridge_ip_reg : ip_reg;
my_udp_chdr_port = bridge_en ? bridge_udp_port : udp_port;
end
</code></pre></div>
</div>
</div>
<div class="register">
<a name="UIO_REGMAP|CHDR_DROPPED"></a>
<h3 class="register">Offset 0x0030: CHDR_DROPPED Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('UIO_REGMAP|CHDR_DROPPED_in')">(<span id="show_UIO_REGMAP|CHDR_DROPPED_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_UIO_REGMAP|CHDR_DROPPED_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|UIO">QSFP_REGMAP|UIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00A000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CHDR_DROPPED</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0030</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000A030
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001A030
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002A030
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003A030
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004A030
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005A030
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006A030
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007A030
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Count the number of Packets dropped that were addressed to the CHDR section.</p></div>
</div>
</div>
<div class="register">
<a name="UIO_REGMAP|CPU_DROPPED"></a>
<h3 class="register">Offset 0x0034: CPU_DROPPED Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('UIO_REGMAP|CPU_DROPPED_in')">(<span id="show_UIO_REGMAP|CPU_DROPPED_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_UIO_REGMAP|CPU_DROPPED_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|UIO">QSFP_REGMAP|UIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00A000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CPU_DROPPED</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0034</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000A034
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001A034
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002A034
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003A034
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004A034
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005A034
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006A034
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007A034
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
<p>Count the number of Packets dropped that were addressed to us, but not to the CHDR section.</p></div>
</div>
</div>
<div class="register">
<a name="UIO_REGMAP|PAUSE"></a>
<h3 class="register">Offset 0x0038: PAUSE Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('UIO_REGMAP|PAUSE_in')">(<span id="show_UIO_REGMAP|PAUSE_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_UIO_REGMAP|PAUSE_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_0">AXI_HPM0_REGMAP|QSFP_0_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#QSFP_REGMAP|UIO">QSFP_REGMAP|UIO</a></td></tr>
<tr><td class="offset_info" align="right"> 0x00A000</td></tr>
</table>
</td>
<td class="outercell" rowspan="8">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">PAUSE</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0038</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120000A038
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_1">AXI_HPM0_REGMAP|QSFP_0_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200010000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120001A038
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_2">AXI_HPM0_REGMAP|QSFP_0_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200020000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120002A038
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_0_3">AXI_HPM0_REGMAP|QSFP_0_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200030000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120003A038
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_0">AXI_HPM0_REGMAP|QSFP_1_0</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200040000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120004A038
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_1">AXI_HPM0_REGMAP|QSFP_1_1</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200050000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120005A038
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_2">AXI_HPM0_REGMAP|QSFP_1_2</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200060000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120006A038
</td></tr>
</table>
</td>
</tr>
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|QSFP_1_3">AXI_HPM0_REGMAP|QSFP_1_3</a></td></tr>
<tr><td class="offset_info" align="right"> 0x1200070000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x120007A038
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file uhd_regs.v.</p>
</div>
<div class="info">
<div class="xmlpmd">
</div>
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..16</td>
<td>
<p><span class="name"><a name="UIO_REGMAP|PAUSE|pause_clear"></a>pause_clear</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause.
<em>Pause clear must be less than pause set or terrible things will happen.</em>
The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only
used with 100Gb ethernet</p></div></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..0</td>
<td>
<p><span class="name"><a name="UIO_REGMAP|PAUSE|pause_set"></a>pause_set</span><span class="attr"> </span></p>
<p><div class="xmlpmd">
<p>If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only
used with 100Gb ethernet</p></div></p>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="regmap">
<a name="VERSIONING_REGS_REGMAP"></a>
<h1 class="regmap">VERSIONING_REGS_REGMAP</h1>
<div class="group"><a name="VERSIONING_REGS_REGMAP|VERSIONING_CONSTANTS"></a><h2 class="group">VERSIONING_CONSTANTS</h2>
<div class="enum">
<a name="VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION"></a>
<h3 class="enum">CPLD_IFC_VERSION Enumeration</h3>
CPLD interface module.<BR/>
For guidance on when to update these revision numbers,
please refer to the register map documentation accordingly:
<li> Current version: <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION">CURRENT_VERSION</a>
<li> Oldest compatible version: <a href="#VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION">OLDEST_COMPATIBLE_VERSION</a>
<li> Version last modified: <a href="#VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED">VERSION_LAST_MODIFIED</a>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' colspan='2'> Value </td>
<td class="l" rowspan='2' colspan='1'> Name </td>
</tr>
<tr class="header2" valign="bottom">
<td class='value'> Dec </td>
<td class='l'> Hex </td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION|CPLD_IFC_CURRENT_VERSION_MINOR'></a>CPLD_IFC_CURRENT_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION|CPLD_IFC_CURRENT_VERSION_BUILD'></a>CPLD_IFC_CURRENT_VERSION_BUILD</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION|CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR'></a>CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION|CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD'></a>CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD</p>
</td>
</tr>
<tr valign="top">
<td class='value'>2</td>
<td class='l'>0x00000002</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION|CPLD_IFC_CURRENT_VERSION_MAJOR'></a>CPLD_IFC_CURRENT_VERSION_MAJOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>2</td>
<td class='l'>0x00000002</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION|CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR'></a>CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>553719817</td>
<td class='l'>0x21011809</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION|CPLD_IFC_VERSION_LAST_MODIFIED_TIME'></a>CPLD_IFC_VERSION_LAST_MODIFIED_TIME</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file cpld_interface_regs.v.
</p>
</div>
<div class="enum">
<a name="VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION"></a>
<h3 class="enum">DB_GPIO_IFC_VERSION Enumeration</h3>
Daughterboard GPIO interface.<BR/>
For guidance on when to update these revision numbers,
please refer to the register map documentation accordingly:
<li> Current version: <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION">CURRENT_VERSION</a>
<li> Oldest compatible version: <a href="#VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION">OLDEST_COMPATIBLE_VERSION</a>
<li> Version last modified: <a href="#VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED">VERSION_LAST_MODIFIED</a>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' colspan='2'> Value </td>
<td class="l" rowspan='2' colspan='1'> Name </td>
</tr>
<tr class="header2" valign="bottom">
<td class='value'> Dec </td>
<td class='l'> Hex </td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION|DB_GPIO_IFC_CURRENT_VERSION_MINOR'></a>DB_GPIO_IFC_CURRENT_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION|DB_GPIO_IFC_CURRENT_VERSION_BUILD'></a>DB_GPIO_IFC_CURRENT_VERSION_BUILD</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION|DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR'></a>DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION|DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD'></a>DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class='l'>0x00000001</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION|DB_GPIO_IFC_CURRENT_VERSION_MAJOR'></a>DB_GPIO_IFC_CURRENT_VERSION_MAJOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class='l'>0x00000001</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION|DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR'></a>DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>537986582</td>
<td class='l'>0x20110616</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION|DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME'></a>DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file db_gpio_interface.v.
</p>
</div>
<div class="enum">
<a name="VERSIONING_REGS_REGMAP|FPGA_VERSION"></a>
<h3 class="enum">FPGA_VERSION Enumeration</h3>
FPGA version.<BR/>
For guidance on when to update these revision numbers,
please refer to the register map documentation accordingly:
<li> Current version: <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION">CURRENT_VERSION</a>
<li> Oldest compatible version: <a href="#VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION">OLDEST_COMPATIBLE_VERSION</a>
<li> Version last modified: <a href="#VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED">VERSION_LAST_MODIFIED</a>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' colspan='2'> Value </td>
<td class="l" rowspan='2' colspan='1'> Name </td>
</tr>
<tr class="header2" valign="bottom">
<td class='value'> Dec </td>
<td class='l'> Hex </td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_BUILD'></a>FPGA_CURRENT_VERSION_BUILD</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_BUILD'></a>FPGA_OLDEST_COMPATIBLE_VERSION_BUILD</p>
</td>
</tr>
<tr valign="top">
<td class='value'>5</td>
<td class='l'>0x00000005</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>7</td>
<td class='l'>0x00000007</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MAJOR'></a>FPGA_CURRENT_VERSION_MAJOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>7</td>
<td class='l'>0x00000007</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>554766864</td>
<td class='l'>0x21111210</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file x4xx.v.
</p>
</div>
<div class="enum">
<a name="VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION"></a>
<h3 class="enum">RF_CORE_100M_VERSION Enumeration</h3>
100 MHz RF core.<BR/>
For guidance on when to update these revision numbers,
please refer to the register map documentation accordingly:
<li> Current version: <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION">CURRENT_VERSION</a>
<li> Oldest compatible version: <a href="#VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION">OLDEST_COMPATIBLE_VERSION</a>
<li> Version last modified: <a href="#VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED">VERSION_LAST_MODIFIED</a>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' colspan='2'> Value </td>
<td class="l" rowspan='2' colspan='1'> Name </td>
</tr>
<tr class="header2" valign="bottom">
<td class='value'> Dec </td>
<td class='l'> Hex </td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION|RF_CORE_100M_CURRENT_VERSION_MINOR'></a>RF_CORE_100M_CURRENT_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION|RF_CORE_100M_CURRENT_VERSION_BUILD'></a>RF_CORE_100M_CURRENT_VERSION_BUILD</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION|RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR'></a>RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION|RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD'></a>RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class='l'>0x00000001</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION|RF_CORE_100M_CURRENT_VERSION_MAJOR'></a>RF_CORE_100M_CURRENT_VERSION_MAJOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class='l'>0x00000001</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION|RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR'></a>RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>537929239</td>
<td class='l'>0x20102617</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION|RF_CORE_100M_VERSION_LAST_MODIFIED_TIME'></a>RF_CORE_100M_VERSION_LAST_MODIFIED_TIME</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file rf_core_100m.v.
</p>
</div>
<div class="enum">
<a name="VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION"></a>
<h3 class="enum">RF_CORE_400M_VERSION Enumeration</h3>
400 MHz RF core.<BR/>
For guidance on when to update these revision numbers,
please refer to the register map documentation accordingly:
<li> Current version: <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION">CURRENT_VERSION</a>
<li> Oldest compatible version: <a href="#VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION">OLDEST_COMPATIBLE_VERSION</a>
<li> Version last modified: <a href="#VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED">VERSION_LAST_MODIFIED</a>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' colspan='2'> Value </td>
<td class="l" rowspan='2' colspan='1'> Name </td>
</tr>
<tr class="header2" valign="bottom">
<td class='value'> Dec </td>
<td class='l'> Hex </td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION|RF_CORE_400M_CURRENT_VERSION_MINOR'></a>RF_CORE_400M_CURRENT_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION|RF_CORE_400M_CURRENT_VERSION_BUILD'></a>RF_CORE_400M_CURRENT_VERSION_BUILD</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION|RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR'></a>RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION|RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD'></a>RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class='l'>0x00000001</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION|RF_CORE_400M_CURRENT_VERSION_MAJOR'></a>RF_CORE_400M_CURRENT_VERSION_MAJOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class='l'>0x00000001</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION|RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR'></a>RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>537929239</td>
<td class='l'>0x20102617</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION|RF_CORE_400M_VERSION_LAST_MODIFIED_TIME'></a>RF_CORE_400M_VERSION_LAST_MODIFIED_TIME</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file rf_core_400m.v.
</p>
</div>
</div>
<div class="group"><a name="VERSIONING_REGS_REGMAP|VERSIONING_REGS"></a><h2 class="group">VERSIONING_REGS</h2>
<div class="enum">
<a name="VERSIONING_REGS_REGMAP|COMPONENTS_INDEXES"></a>
<h3 class="enum">COMPONENTS_INDEXES Enumeration</h3>
This enum contains indexes for all the components in the X410
(both common and app-specific) which version information is
desired to be available for compatibility tracking purposes.<BR/>
<table border="1">
<tr><th>Description</th> <th>Index range</th> <th>Max # of components</th></tr>
<tr><td>Common components</td> <td>0 to 23</td> <td>24</td></tr>
<tr><td>UHD-specific components</td> <td>24 to 43</td> <td>20</td></tr>
<tr><td>LV-specific components</td> <td>44 to 63</td> <td>20</td></tr>
</table>
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
<td class='value' > Value </td>
<td class="l" colspan='1'> Name </td>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|COMPONENTS_INDEXES|FPGA_VERSION_INDEX'></a>FPGA_VERSION_INDEX</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|COMPONENTS_INDEXES|CPLD_IFC_INDEX'></a>CPLD_IFC_INDEX</p>
</td>
</tr>
<tr valign="top">
<td class='value'>2</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|COMPONENTS_INDEXES|DB0_RF_CORE_INDEX'></a>DB0_RF_CORE_INDEX</p>
</td>
</tr>
<tr valign="top">
<td class='value'>3</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|COMPONENTS_INDEXES|DB1_RF_CORE_INDEX'></a>DB1_RF_CORE_INDEX</p>
</td>
</tr>
<tr valign="top">
<td class='value'>4</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|COMPONENTS_INDEXES|DB0_GPIO_IFC_INDEX'></a>DB0_GPIO_IFC_INDEX</p>
</td>
</tr>
<tr valign="top">
<td class='value'>5</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|COMPONENTS_INDEXES|DB1_GPIO_IFC_INDEX'></a>DB1_GPIO_IFC_INDEX</p>
</td>
</tr>
</table>
<p class="enum_info">
This enumerated type is defined in HDL source file x4xx_versioning_regs.v.
</p>
</div>
<div class="register">
<a name="VERSIONING_REGS_REGMAP|CURRENT_VERSION"></a>
<h3 class="register">Offset 0x0000: CURRENT_VERSION(63:0) Register Array (R)</h3>
<a class="sh_addrs" href="javascript:sa('VERSIONING_REGS_REGMAP|CURRENT_VERSION_in')">(<span id="show_VERSIONING_REGS_REGMAP|CURRENT_VERSION_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_VERSIONING_REGS_REGMAP|CURRENT_VERSION_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|VERSIONING_REGS">CORE_REGS_REGMAP|VERSIONING_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000C00</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">CURRENT_VERSION</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0000 + i*0x10</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0C00 + i*0x10
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info"><B>Initial Values</B><BR/>
<table>
<tr><td>default</td><td>=></td><td>0x00000000</td></tr>
</table>
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_versioning_regs.v.<BR/>
It uses RegType <b>VERSION_TYPE</b> which is defined in HDL source file x4xx_versioning_regs.v.</p>
</div>
<div class="info">
Component's current version.<BR/>
This register contains the current component's version implemented in HDL.
The current version shall be used to detect a component being too
old for the driver/software:<BR/>
<b>SW oldest compatible version > Component's current version --> Component is too old.</b>
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..23</td>
<td>
<p><span class="name"><a name="VERSIONING_REGS_REGMAP|CURRENT_VERSION|MAJOR"></a>MAJOR</span><span class="attr"> (initialvalue=0)</span></p>
<p>Major number (max = 511): an increase reflects a breaking change.<BR/>
<b>IMPORTANT!</b> <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MAJOR">MAJOR</a> must always remain in sync between the component's
<a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION">CURRENT_VERSION</a> and <a href="#VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION">OLDEST_COMPATIBLE_VERSION</a> registers.<BR/><BR/>
Update <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MAJOR">MAJOR</a> when:
<li>the component has changed and requires a software changes as a result.
<li>the component's bitfields/registers have been modified or deleted.
<li>the component's bitfields/registers are initialized to different value (unexpected by software).
<li>new bitfields/registers are added that require software interaction for the component to operate.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">22..12</td>
<td>
<p><span class="name"><a name="VERSIONING_REGS_REGMAP|CURRENT_VERSION|MINOR"></a>MINOR</span><span class="attr"> (initialvalue=0)</span></p>
<p>Minor number (max = 2047): an increase reflects a non-breaking change that the driver should be aware of.<BR/><BR/>
Update <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MINOR">MINOR</a> when:
<li>a new feature is added to the component, which does not conflict with the driver.
<li>minor implementation changes were made to the component which are worth tracking.
<li>the component has added new bitfields/registers that do not require software interaction
(i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to
previously undefined bits).
<li><a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MAJOR">MAJOR</a> is updated (reset <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MINOR">MINOR</a> to 0).</p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="VERSIONING_REGS_REGMAP|CURRENT_VERSION|BUILD"></a>BUILD</span><span class="attr"> (initialvalue=0)</span></p>
<p>Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
but that should not impact the component's behavior <BR/>
Eventually, this number is intended to be automatically incremented for any new build.<BR/><BR/>
Meanwhile, update <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|BUILD">BUILD</a> when:
<li>the component's source code changes are not captured by <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MAJOR">MAJOR</a> or <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MINOR">MINOR</a>.
<li><a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MINOR">MINOR</a> or <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MAJOR">MAJOR</a> are updated (reset <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|BUILD">BUILD</a> to 0).</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION"></a>
<h3 class="register">Offset 0x0004: OLDEST_COMPATIBLE_VERSION(63:0) Register Array (R)</h3>
<a class="sh_addrs" href="javascript:sa('VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION_in')">(<span id="show_VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|VERSIONING_REGS">CORE_REGS_REGMAP|VERSIONING_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000C00</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">OLDEST_COMPATIBLE_VERSION</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0004 + i*0x10</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0C04 + i*0x10
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info"><B>Initial Values</B><BR/>
<table>
<tr><td>default</td><td>=></td><td>0x00000000</td></tr>
</table>
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_versioning_regs.v.<BR/>
It uses RegType <b>VERSION_TYPE</b> which is defined in HDL source file x4xx_versioning_regs.v.</p>
</div>
<div class="info">
Component's oldest compatible version.<BR/>
This register contains the oldest compatible component's version, that is the oldest
component's implementation that is compatible with the current implementation.<BR/>
The oldest compatible version shall be used to detect a component being too
new for the driver/software:<BR/>
<b>SW current version < Component's oldest compatible version --> Component is too new.</b>
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..23</td>
<td>
<p><span class="name"><a name="VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION|MAJOR"></a>MAJOR</span><span class="attr"> (initialvalue=0)</span></p>
<p>Major number (max = 511): an increase reflects a breaking change.<BR/>
<b>IMPORTANT!</b> <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MAJOR">MAJOR</a> must always remain in sync between the component's
<a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION">CURRENT_VERSION</a> and <a href="#VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION">OLDEST_COMPATIBLE_VERSION</a> registers.<BR/><BR/>
Update <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MAJOR">MAJOR</a> when:
<li>the component has changed and requires a software changes as a result.
<li>the component's bitfields/registers have been modified or deleted.
<li>the component's bitfields/registers are initialized to different value (unexpected by software).
<li>new bitfields/registers are added that require software interaction for the component to operate.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">22..12</td>
<td>
<p><span class="name"><a name="VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION|MINOR"></a>MINOR</span><span class="attr"> (initialvalue=0)</span></p>
<p>Minor number (max = 2047): an increase reflects a non-breaking change that the driver should be aware of.<BR/><BR/>
Update <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MINOR">MINOR</a> when:
<li>a new feature is added to the component, which does not conflict with the driver.
<li>minor implementation changes were made to the component which are worth tracking.
<li>the component has added new bitfields/registers that do not require software interaction
(i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to
previously undefined bits).
<li><a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MAJOR">MAJOR</a> is updated (reset <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MINOR">MINOR</a> to 0).</p>
</td>
</tr>
<tr valign="top">
<td class="bits">11..0</td>
<td>
<p><span class="name"><a name="VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION|BUILD"></a>BUILD</span><span class="attr"> (initialvalue=0)</span></p>
<p>Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
but that should not impact the component's behavior <BR/>
Eventually, this number is intended to be automatically incremented for any new build.<BR/><BR/>
Meanwhile, update <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|BUILD">BUILD</a> when:
<li>the component's source code changes are not captured by <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MAJOR">MAJOR</a> or <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MINOR">MINOR</a>.
<li><a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MINOR">MINOR</a> or <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|MAJOR">MAJOR</a> are updated (reset <a href="#VERSIONING_REGS_REGMAP|CURRENT_VERSION|BUILD">BUILD</a> to 0).</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED"></a>
<h3 class="register">Offset 0x0008: VERSION_LAST_MODIFIED(63:0) Register Array (R)</h3>
<a class="sh_addrs" href="javascript:sa('VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED_in')">(<span id="show_VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|VERSIONING_REGS">CORE_REGS_REGMAP|VERSIONING_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000C00</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">VERSION_LAST_MODIFIED</td></tr>
<tr><td class="offset_info" align="right"> offset=0x0008 + i*0x10</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0C08 + i*0x10
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_versioning_regs.v.<BR/>
It uses RegType <b>TIMESTAMP_TYPE</b> which is defined in HDL source file x4xx_versioning_regs.v.</p>
</div>
<div class="info">
Component's versions update time.<BR/>
This register provides the time stamp for the last modification to
the component's versions (current & oldest compatible).
The time stamp is provided in hexadecimal format: 0xYYMMDDHH.<BR/>
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name"><a name="VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED|YY"></a>YY</span><span class="attr"> </span></p>
<p>This is the year number after 2000 (e.g. 2019 = 0x19).</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..16</td>
<td>
<p><span class="name"><a name="VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED|MM"></a>MM</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name"><a name="VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED|DD"></a>DD</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..0</td>
<td>
<p><span class="name"><a name="VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED|HH"></a>HH</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="VERSIONING_REGS_REGMAP|RESERVED"></a>
<h3 class="register">Offset 0x000C: RESERVED(63:0) Register Array (R)</h3>
<a class="sh_addrs" href="javascript:sa('VERSIONING_REGS_REGMAP|RESERVED_in')">(<span id="show_VERSIONING_REGS_REGMAP|RESERVED_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_VERSIONING_REGS_REGMAP|RESERVED_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|VERSIONING_REGS">CORE_REGS_REGMAP|VERSIONING_REGS</a></td></tr>
<tr><td class="offset_info" align="right"> 0x000C00</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RESERVED</td></tr>
<tr><td class="offset_info" align="right"> offset=0x000C + i*0x10</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info"> 0x10000A0C0C + i*0x10
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_versioning_regs.v.<BR/>
It uses RegType <b>RESERVED_TYPE</b> which is defined in HDL source file x4xx_versioning_regs.v.</p>
</div>
<div class="info">
Reserved.<BR/>
</div>
</div>
</div>
</div>
<div class="regmap">
<a name="XGE_MAC_REGMAP"></a>
<h1 class="regmap">XGE_MAC_REGMAP</h1>
<div class="xmlpmd">
</div>
<div class="group"><a name="XGE_MAC_REGMAP|OPENCORE_XGE_REGISTERS"></a><h2 class="group">OPENCORE_XGE_REGISTERS</h2>
<div class="xmlpmd">
<p>10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf</p></div>
</div>
</div>
</body>
</HTML>