]> Release 14.1 Trace (lin64)Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved./opt/Xilinx/14.1/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -e 10 -s 3 -n 3 -fastpaths -xml b200.twx b200.ncd -o b200.twr b200.pcf b200.ncdb200.ncdb200.pcfb200.pcfxc6slx75C-3PRODUCTION 1.21 2012-04-231103INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.TS_codec_main_clk = PERIOD TIMEGRP "codec_main_clk" 25 ns HIGH 50%;000000016.000Component Switching Limit Checks: TS_codec_main_clk = PERIOD TIMEGRP "codec_main_clk" 25 ns HIGH 50%;TS_IFCLK = PERIOD TIMEGRP "IFCLK" 10 ns HIGH 50%;0000000Component Switching Limit Checks: TS_IFCLK = PERIOD TIMEGRP "IFCLK" 10 ns HIGH 50%;TS_codec_data_clk_p = PERIOD TIMEGRP "codec_data_clk_p" 16.276 ns HIGH 50%;00000001.639Component Switching Limit Checks: TS_codec_data_clk_p = PERIOD TIMEGRP "codec_data_clk_p" 16.276 ns HIGH 50%;TS_gen_clks_clkfx = PERIOD TIMEGRP "gen_clks_clkfx" TS_codec_main_clk / 2.5 HIGH 50%;4890322009931212.189Paths for end point slave_fifo32/EP_READY1 (OLOGIC_X4Y173.D1), 1 path -2.189slave_fifo32/EP_READYslave_fifo32/EP_READY112.263-0.30910.0000.235slave_fifo32/EP_READYslave_fifo32/EP_READY10ILOGIC_X17Y55.CLK0gpif_clkILOGIC_X17Y55.Q4Tickq0.992slave_fifo32/EP_READYslave_fifo32/EP_READYOLOGIC_X4Y173.D1net210.468slave_fifo32/EP_READYOLOGIC_X4Y173.CLK0Todck0.803slave_fifo32/EP_READY1slave_fifo32/EP_READY11.79510.46812.263gpif_clk14.685.4Paths for end point slave_fifo32/EP_WMARK1 (OLOGIC_X2Y175.D1), 1 path -1.341slave_fifo32/EP_WMARKslave_fifo32/EP_WMARK111.0290.07710.0000.235slave_fifo32/EP_WMARKslave_fifo32/EP_WMARK10ILOGIC_X17Y78.CLK0gpif_clkILOGIC_X17Y78.Q4Tickq0.992slave_fifo32/EP_WMARKslave_fifo32/EP_WMARKOLOGIC_X2Y175.D1net29.234slave_fifo32/EP_WMARKOLOGIC_X2Y175.CLK0Todck0.803slave_fifo32/EP_WMARK1slave_fifo32/EP_WMARK11.7959.23411.029gpif_clk16.383.7Component Switching Limit Checks: TS_gen_clks_clkfx = PERIOD TIMEGRP "gen_clks_clkfx" TS_codec_main_clk / 2.5 HIGH 50%;1codec_main_clk_ncodec_main_clk_n12.189codec_main_clk_p12.189codec_main_clk_pcodec_main_clk_n12.189codec_main_clk_p12.18923530353004890301238816.00062.500Tue Jan 29 17:12:06 2013 TraceTrace Settings Peak Memory Usage: 536 MB