clk clk reset reset set_stb set_stb set_addr[15:0] set_addr[15:0] HEXRADIX set_data[31:0] set_data[31:0] HEXRADIX local_addr[7:0] local_addr[7:0] New Divider label 128 128 255 230 230 230 Input Port 0 label HEXRADIX i_tdata[64:0] i_tdata[64:0] HEXRADIX i_tvalid i_tvalid i_tready i_tready o_tdata[64:0] o_tdata[64:0] HEXRADIX o_tvalid o_tvalid o_tready o_tready New Divider label 128 128 255 230 230 230 Input Port 1 label HEXRADIX i_tdata[64:0] i_tdata[64:0] HEXRADIX i_tvalid i_tvalid i_tready i_tready o_tdata[64:0] o_tdata[64:0] HEXRADIX o_tvalid o_tvalid o_tready o_tready New Divider label 128 128 255 230 230 230 Input Port 2 label i_tdata[64:0] i_tdata[64:0] i_tvalid i_tvalid i_tready i_tready o_tdata[64:0] o_tdata[64:0] o_tvalid o_tvalid o_tready o_tready New Divider label 128 128 255 230 230 230 Input Port 3 label i_tdata[64:0] i_tdata[64:0] i_tvalid i_tvalid i_tready i_tready o_tdata[64:0] o_tdata[64:0] o_tvalid o_tvalid o_tready o_tready New Divider label 128 128 255 230 230 230 Output Port 0 label HEXRADIX i_tdata[64:0] i_tdata[64:0] HEXRADIX i_tvalid i_tvalid i_tready i_tready o_tdata[64:0] o_tdata[64:0] HEXRADIX o_tvalid o_tvalid o_tready o_tready New Divider label 128 128 255 230 230 230 Output Port 1 label HEXRADIX i_tdata[64:0] i_tdata[64:0] HEXRADIX i_tvalid i_tvalid i_tready i_tready o_tdata[64:0] o_tdata[64:0] HEXRADIX o_tvalid o_tvalid o_tready o_tready New Divider label 128 128 255 230 230 230 Output Port 2 label i_tdata[64:0] i_tdata[64:0] i_tvalid i_tvalid i_tready i_tready o_tdata[64:0] o_tdata[64:0] o_tvalid o_tvalid o_tready o_tready New Divider label 128 128 255 230 230 230 Output Port 3 label i_tdata[64:0] i_tdata[64:0] i_tvalid i_tvalid i_tready i_tready o_tdata[64:0] o_tdata[64:0] o_tvalid o_tvalid o_tready o_tready New Divider label 128 128 255 230 230 230