/////////////////////////////////////////////////////////////////////// // File: CRC32_D8.v // Date: Fri Feb 8 19:26:59 2008 // // Copyright (C) 1999-2003 Easics NV. // This source file may be used and distributed without restriction // provided that this copyright statement is not removed from the file // and that any derivative work contains the original copyright notice // and the associated disclaimer. // // THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS // OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED // WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. // // Purpose: Verilog module containing a synthesizable CRC function // * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) // * data width: 8 // // Info: tools@easics.be // http://www.easics.com /////////////////////////////////////////////////////////////////////// //module CRC32_D8; // polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) // data width: 8 // convention: the first serial data bit is D[7] function [31:0] nextCRC32_D8; input [7:0] Data; input [31:0] CRC; reg [7:0] D; reg [31:0] C; reg [31:0] NewCRC; begin D = Data; C = CRC; NewCRC[0] = D[6] ^ D[0] ^ C[24] ^ C[30]; NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[30] ^ C[31]; NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[26] ^ C[30] ^ C[31]; NewCRC[3] = D[7] ^ D[3] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ C[27] ^ C[31]; NewCRC[4] = D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ C[27] ^ C[28] ^ C[30]; NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ C[31]; NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30] ^ C[31]; NewCRC[7] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ C[27] ^ C[29] ^ C[31]; NewCRC[8] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[24] ^ C[25] ^ C[27] ^ C[28]; NewCRC[9] = D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[1] ^ C[25] ^ C[26] ^ C[28] ^ C[29]; NewCRC[10] = D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[24] ^ C[26] ^ C[27] ^ C[29]; NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[24] ^ C[25] ^ C[27] ^ C[28]; NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[24] ^ C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30]; NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[25] ^ C[26] ^ C[27] ^ C[29] ^ C[30] ^ C[31]; NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[26] ^ C[27] ^ C[28] ^ C[30] ^ C[31]; NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[27] ^ C[28] ^ C[29] ^ C[31]; NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[24] ^ C[28] ^ C[29]; NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[25] ^ C[29] ^ C[30]; NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[26] ^ C[30] ^ C[31]; NewCRC[19] = D[7] ^ D[3] ^ C[11] ^ C[27] ^ C[31]; NewCRC[20] = D[4] ^ C[12] ^ C[28]; NewCRC[21] = D[5] ^ C[13] ^ C[29]; NewCRC[22] = D[0] ^ C[14] ^ C[24]; NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[15] ^ C[24] ^ C[25] ^ C[30]; NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[16] ^ C[25] ^ C[26] ^ C[31]; NewCRC[25] = D[3] ^ D[2] ^ C[17] ^ C[26] ^ C[27]; NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[18] ^ C[24] ^ C[27] ^ C[28] ^ C[30]; NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[19] ^ C[25] ^ C[28] ^ C[29] ^ C[31]; NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[20] ^ C[26] ^ C[29] ^ C[30]; NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[21] ^ C[27] ^ C[30] ^ C[31]; NewCRC[30] = D[7] ^ D[4] ^ C[22] ^ C[28] ^ C[31]; NewCRC[31] = D[5] ^ C[23] ^ C[29]; nextCRC32_D8 = NewCRC; end endfunction //endmodule