analog.com user util_axis_fifo 1.0 S_AXIS TVALID s_axis_valid TREADY s_axis_ready TDATA s_axis_data M_AXIS TVALID m_axis_valid TREADY m_axis_ready TDATA m_axis_data M_AXIS_signal_clock M_AXIS_signal_clock CLK m_axis_aclk ASSOCIATED_BUSIF M_AXIS ASSOCIATED_RESET m_axis_aresetn M_AXIS_signal_reset M_AXIS_signal_reset RST m_axis_aresetn POLARITY ACTIVE_LOW S_AXIS_signal_clock S_AXIS_signal_clock CLK s_axis_aclk ASSOCIATED_BUSIF S_AXIS ASSOCIATED_RESET m_axis_aresetn S_AXIS_signal_reset S_AXIS_signal_reset RST m_axis_aresetn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_axis_fifo xilinx_anylanguagesynthesis_view_fileset xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_axis_fifo xilinx_anylanguagebehavioralsimulation_view_fileset xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset m_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_data out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_level out 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_data in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_empty out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_room out 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation DATA_WIDTH Data Width 64 ASYNC_CLK Async Clk 1 ADDRESS_WIDTH Address Width 4 S_AXIS_REGISTERED S Axis Registered 1 xilinx_anylanguagesynthesis_view_fileset sync_gray.v verilogSource sync_bits.v verilogSource address_gray_pipelined.v verilogSource address_sync.v verilogSource util_axis_fifo.v verilogSource CHECKSUM_239993f9 xilinx_anylanguagebehavioralsimulation_view_fileset sync_gray.v verilogSource USED_IN_ipstatic sync_bits.v verilogSource USED_IN_ipstatic address_gray_pipelined.v verilogSource USED_IN_ipstatic address_sync.v verilogSource USED_IN_ipstatic util_axis_fifo.v verilogSource USED_IN_ipstatic xilinx_xpgui_view_fileset xgui/util_axis_fifo_v1_0.tcl tclSource CHECKSUM_13c68e4c XGUI_VERSION_2 util_axis_fifo_v1_0 DATA_WIDTH Data Width 64 ASYNC_CLK Async Clk 1 ADDRESS_WIDTH Address Width 4 S_AXIS_REGISTERED S Axis Registered 1 Component_Name util_axis_fifo_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l artix7 artix7l aartix7 qartix7 zynq qzynq azynq virtexu kintexuplus zynquplus kintexu virtexuplus /Analog_Devices util_axis_fifo_v1_0 Analog Devices http://www.analog.com 1 2017-04-20T23:50:31Z 2015.4