ettus.com ip axi_regfile 1.0 S_AXI AWADDR S_AXI_AWADDR AWVALID S_AXI_AWVALID AWREADY S_AXI_AWREADY WDATA S_AXI_WDATA WSTRB S_AXI_WSTRB WVALID S_AXI_WVALID WREADY S_AXI_WREADY BRESP S_AXI_BRESP BVALID S_AXI_BVALID BREADY S_AXI_BREADY ARADDR S_AXI_ARADDR ARVALID S_AXI_ARVALID ARREADY S_AXI_ARREADY RDATA S_AXI_RDATA RRESP S_AXI_RRESP RVALID S_AXI_RVALID RREADY S_AXI_RREADY S_AXI_ACLK CLK S_AXI_ACLK ASSOCIATED_BUSIF S_AXI ASSOCIATED_RESET S_AXI_ARESETN S_AXI_ARESETN RST S_AXI_ARESETN POLARITY ACTIVE_LOW S_AXI regs 0 4096 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL axi_regfile xilinx_anylanguagesynthesis_view_fileset viewChecksum 876922da xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL axi_regfile xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 876922da xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 012f1d4f regs out 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_ARESETN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_AWADDR in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_AWVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_AWREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_WDATA in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_WSTRB in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_WVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_WREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_BRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_BVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_BREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_ARADDR in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_ARVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_ARREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_RDATA out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_RRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_RVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_RREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 NUM_REGS Num Regs 16 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axi_regfile.vhd vhdlSource CHECKSUM_876922da xilinx_anylanguagebehavioralsimulation_view_fileset axi_regfile.vhd vhdlSource USED_IN_ipstatic xilinx_xpgui_view_fileset xgui/axi_regfile_v1_0.tcl tclSource CHECKSUM_012f1d4f XGUI_VERSION_2 axi_regfile_v1_0 NUM_REGS Num Regs 16 Component_Name axi_regfile_v1_0 zynq /EttusResearch axi_regfile_v1_0 2 2017-06-02T21:40:33Z usrp3/lib/vivado_ipi/axi_regfile 2015.4