clk clk reset reset set_stb set_stb set_addr[15:0] set_addr[15:0] HEXRADIX set_data[31:0] set_data[31:0] HEXRADIX in_tdata[63:0] in_tdata[63:0] HEXRADIX in_tuser[3:0] in_tuser[3:0] HEXRADIX in_tvalid in_tvalid in_tready in_tready in_tlast in_tlast vita_tdata[63:0] vita_tdata[63:0] HEXRADIX vita_tvalid vita_tvalid vita_tready vita_tready vita_tlast vita_tlast zpu_tdata[63:0] zpu_tdata[63:0] HEXRADIX zpu_tuser[3:0] zpu_tuser[3:0] HEXRADIX zpu_tvalid zpu_tvalid zpu_tready zpu_tready zpu_tlast zpu_tlast xo_tdata[63:0] xo_tdata[63:0] HEXRADIX xo_tuser[3:0] xo_tuser[3:0] HEXRADIX xo_tvalid xo_tvalid xo_tready xo_tready xo_tlast xo_tlast xo_pre_tdata[63:0] xo_pre_tdata[63:0] HEXRADIX xo_pre_tuser[3:0] xo_pre_tuser[3:0] HEXRADIX xo_pre_tlast xo_pre_tlast xo_pre_tvalid xo_pre_tvalid xo_pre_tready xo_pre_tready state[2:0] state[2:0] HEXRADIX header_ram_addr[3:0] header_ram_addr[3:0] HEXRADIX header_done header_done out_tlast out_tlast is_eth_dst_addr is_eth_dst_addr is_eth_broadcast is_eth_broadcast is_eth_type_ipv4 is_eth_type_ipv4 is_ipv4_dst_addr is_ipv4_dst_addr is_ipv4_proto_udp is_ipv4_proto_udp is_udp_dst_ports[1:0] is_udp_dst_ports[1:0] my_mac[47:0] my_mac[47:0] HEXRADIX my_ip[31:0] my_ip[31:0] HEXRADIX my_port0[15:0] my_port0[15:0] HEXRADIX my_port1[15:0] my_port1[15:0] HEXRADIX rd_addr[9:0] rd_addr[9:0] HEXRADIX empty_reg empty_reg read read dob[68:0] dob[68:0]