xilinx.com xci unknown 1.0 dds ACTIVE_LOW 100000000 0 0.000 0 1 1 1 1 1 1 1 1 100000000 0 0 1 0 0 undef 0.000 4 0 0 0 100000000 0 0 1 0 0 undef 0.000 4 0 0 0 100000000 0 0 1 0 0 undef 0.000 8 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 32 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 15 1 0 9 0 32 1 0 32 1 0 0 0 0 2 0 16 16 1 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 1 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 0 0 0 64 0 1 1 1 kintex7 Unit_Circle 1 dds Not_Required 214 Maximal 0.4 Coregen false true true true 15 Auto Not_Required Not_Required Block_ROM Standard 9 false false None Twos_Complement Area 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sine_and_Cosine 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 false Hardware_Parameters Phase_Generator_and_SIN_COS_LUT Programmable 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 Programmable false On_Vector Not_Required 1 45 false 1 kintex7 xc7k410t ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 18 TRUE . . 2019.1 OUT_OF_CONTEXT