#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
#
#   This pipeline is used to test building  the FPGA and CPLD for each pull
#   request.
#
#   See https://aka.ms/yaml for pipeline YAML documentation.
#

trigger:
- none

# Filter for target branches and paths on PRs. See:
# https://docs.microsoft.com/en-us/azure/devops/pipelines/build/triggers?view=azure-devops&tabs=yaml#pr-triggers
pr:
  branches:
    include:
    - master
  paths:
    include:
    - fpga/usrp3/lib
    - fpga/usrp3/tools
    - fpga/usrp3/top/x400
    - fpga/.ci

jobs:
# -------------------------------------------------------------------
# Build XG FPGA (100 MHz)
# -------------------------------------------------------------------
- template: templates/fpga_build.yml
  parameters:
    target: X410_XG_100
    debug: true  # to be able to debug any failed attempts
    clean: false # for speedup of PR testing
    timeout: 480

# -------------------------------------------------------------------
# Build X4 FPGA (200 MHz)
# -------------------------------------------------------------------
- template: templates/fpga_build.yml
  parameters:
    target: X410_X4_200
    debug: true  # to be able to debug any failed attempts
    clean: false # for speedup of PR testing
    timeout: 480

# -------------------------------------------------------------------
# Build C1 FPGA (400 MHz)
# -------------------------------------------------------------------
- template: templates/fpga_build.yml
  parameters:
    target: X410_C1_400
    debug: true  # to be able to debug any failed attempts
    clean: false # for speedup of PR testing
    timeout: 480

# -------------------------------------------------------------------
# Make CPLD
# -------------------------------------------------------------------
#- template: templates/mb_cpld_build.yml
#  parameters:
#    debug: true  # to be able to debug any failed attempts

# -------------------------------------------------------------------
# Make ZBX CPLD
# -------------------------------------------------------------------
#- template: templates/zbx_cpld_build.yml
#  parameters:
#    debug: true  # to be able to debug any failed attempts

# -------------------------------------------------------------------
# Build IP
# -------------------------------------------------------------------
- job: IP
  displayName: 'Build IP'
  pool:
    name: de-dre-lab
    demands:
    - ettus_fpga_build
    - vivado2019.1
  timeoutInMinutes: 120
  steps:
    - checkout: self
      clean: false

    - bash: |
        python3 cleanup_incomplete_ip_builds.py -d $BUILD_SOURCESDIRECTORY/fpga/usrp3/top/x400
      workingDirectory: fpga/.ci/scripts/
      displayName: 'Incomplete IP Cleanup'

    # Delete everything except for the build-ip directory, which is expected to
    # remain for speed-up.
    - bash: |
        git clean -xdff -e build-ip
      displayName: 'git clean'

    - bash: |
        source setupenv.sh
        make X410_IP
      workingDirectory: fpga/usrp3/top/x400

    - publish: fpga/usrp3/top/x400/build-ip
      artifact: 'IP ($(System.JobAttempt))'
      condition: failed()

    - publish: fpga/usrp3/top/x400/build-ip
      artifact: 'IP'
      condition: succeeded()

    - template: templates/check_clean_repo_steps.yml