// This tests sends 5 packets, injecting a bit error in two of them
// to verify the Rx CRC check works. The corresponding RMON statistics
// counter is finally checked to verify that the error was registered

// Read from register 24 to confirm that Rx CRC check is enabled
03 00 18 00 01 ff ff

// Set speed to 1000 Mbps
01 00 22 00 04

// Setup Tx and Rx MAC addresses and type field to "IP"
// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00

//--- Packets #0 & 1 --------------------------------------------------------

// Transmit a 200-byte frame 1 time - and expect it to be received again!
20 00 C8 00 01

// Wait (indefinitely) for missing Rx packets
22 00 00 

// Transmit a 200-byte frame 1 time - but expect to receive it with error!
25 00 C8 00 01

// Inject a single bit error in the packet (data bit 0) - this will cause a CRC error
23 00 01

// Wait (indefinitely) for missing Rx packets
22 00 00 

//--- Packets #2 & 3 --------------------------------------------------------

// Transmit a 200-byte frame 1 time - and expect it to be received again!
20 00 C8 00 01

// Wait (indefinitely) for missing Rx packets
22 00 00 

// Transmit a 200-byte frame 1 time - but expect to receive it with error!
25 00 C8 00 01

// Inject a single bit error in the packet (data bit 7) - this will cause a CRC error
23 00 80

// Wait (indefinitely) for missing Rx packets
22 00 00 

//--- Packets #4 & 5 --------------------------------------------------------

// Transmit a 200-byte frame 1 time - and expect it to be received again!
20 00 C8 00 01

// Wait (indefinitely) for missing Rx packets
22 00 00 

// Transmit a 200-byte frame 1 time - but don't expect it to be received again!
21 00 C8 00 01

// Inject a single bit error in the packet (RxEn) - this will cause a packet discard!
// (because it happens early in the packet)
23 01 00

// Wait (indefinitely) for missing Rx packets
22 00 00 

//--- Packets #6 & 7 --------------------------------------------------------

// Transmit a 200-byte frame 1 time - and expect it to be received again!
20 00 C8 00 01

// Wait (indefinitely) for missing Rx packets
22 00 00 

// Transmit a 200-byte frame 1 time - but don't expect it to be received again!
21 00 C8 00 01

// Inject a single bit error in the packet (RxEr)
23 02 00

// Wait (indefinitely) for missing Rx packets
22 00 00 

//--- Packet #8 -------------------------------------------------------------

// Transmit a 200-byte frame 1 time - and expect it to be received again!
20 00 C8 00 01

// Wait (indefinitely) for missing Rx packets
22 00 00 

//---------------------------------------------------------------------------

// Set CPU_rd_addr to address RxCRCErrCounter
01 00 1C 00 05

// Assert CPU_rd_apply
01 00 1D 00 01

// Kill a little time while waiting for CPU_rd_grant to assert...
02 00 1E
02 00 1E
02 00 1E
02 00 1E

// Confirm that CPU_rd_grant is asserted
03 00 1E 00 01 ff ff

// Read & check low part of RxCRCErrCounter (0x0002)
03 00 1F 00 02 ff ff

// Read & check high part of RxCRCErrCounter (0x0000)
03 00 20 00 00 ff ff

// Negate CPU_rd_apply
01 00 1D 00 00

//---------------------------------------------------------------------------

// Set CPU_rd_addr to address RxTooShortTooLongCounter
01 00 1C 00 07

// Assert CPU_rd_apply
01 00 1D 00 01

// Kill a little time while waiting for CPU_rd_grant to assert...
02 00 1E
02 00 1E
02 00 1E
02 00 1E

// Confirm that CPU_rd_grant is asserted
03 00 1E 00 01 ff ff

// Read & check low part of RxTooShortTooLongCounter (0x0002)
03 00 1F 00 02 ff ff

// Read & check high part of RxTooShortTooLongCounter (0x0000)
03 00 20 00 00 ff ff

// Negate CPU_rd_apply
01 00 1D 00 00


// Halt
FF