From fe6c37c430461b33dd6ba0fd19955143a916044c Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Sun, 25 Mar 2012 12:46:29 -0700
Subject: b100: cleanup redundant logic for slwr and slrd
---
usrp2/gpif/slave_fifo.v | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'usrp2')
diff --git a/usrp2/gpif/slave_fifo.v b/usrp2/gpif/slave_fifo.v
index a8101d376..edfdd7756 100644
--- a/usrp2/gpif/slave_fifo.v
+++ b/usrp2/gpif/slave_fifo.v
@@ -227,8 +227,8 @@ module slave_fifo
assign sloe = ~{(state == STATE_DATA_TX) | (state == STATE_CTRL_TX) | (state == STATE_DATA_TX_SLOE) | (state == STATE_CTRL_TX_SLOE)};
//"read" and "write" here are from the master's point of view;
//so "read" means "transmit" and "write" means "receive"
- assign slwr = ~{(state == STATE_DATA_RX && data_rx_src_rdy && data_rx_dst_rdy) || (state == STATE_CTRL_RX && ctrl_rx_src_rdy && ctrl_rx_dst_rdy)};
- assign slrd = ~{(state == STATE_DATA_TX && data_tx_src_rdy && data_tx_dst_rdy) || (state == STATE_CTRL_TX && ctrl_tx_src_rdy && ctrl_tx_dst_rdy)};
+ assign slwr = ~{(data_rx_src_rdy && data_rx_dst_rdy) || (ctrl_rx_src_rdy && ctrl_rx_dst_rdy)};
+ assign slrd = ~{(data_tx_src_rdy && data_tx_dst_rdy) || (ctrl_tx_src_rdy && ctrl_tx_dst_rdy)};
wire pktend_ctrl, pktend_data;
assign pktend_ctrl = ((~ctrl_rx_src_rdy | gpif_d_out_ctrl[17]) & (state == STATE_CTRL_RX));
--
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