From fc32fa87bc579dfcb04a7a404e6785ac0dc86949 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 24 Mar 2010 16:36:16 -0700 Subject: Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround --- usrp2/vrt/vita_rx_control.v | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'usrp2') diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v index 2e96e6d42..669b8299d 100644 --- a/usrp2/vrt/vita_rx_control.v +++ b/usrp2/vrt/vita_rx_control.v @@ -155,7 +155,13 @@ module vita_rx_control ibs_state <= IBS_RUNNING; end end // else: !if(full) - IBS_OVERRUN, IBS_LATECMD, IBS_BROKENCHAIN : + IBS_OVERRUN : + if(sample_fifo_in_rdy) + ibs_state <= IBS_IDLE; + IBS_LATECMD : + if(sample_fifo_in_rdy) + ibs_state <= IBS_IDLE; + IBS_BROKENCHAIN : if(sample_fifo_in_rdy) ibs_state <= IBS_IDLE; endcase // case(ibs_state) -- cgit v1.2.3