From fd4bdced70e5089434ec736b5938456219bda068 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 11 May 2010 17:20:06 -0700 Subject: reverting logic clean up which should have made timing better, but made it worse instead --- usrp2/control_lib/settings_bus.v | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) (limited to 'usrp2') diff --git a/usrp2/control_lib/settings_bus.v b/usrp2/control_lib/settings_bus.v index aec179516..fc960e456 100644 --- a/usrp2/control_lib/settings_bus.v +++ b/usrp2/control_lib/settings_bus.v @@ -10,7 +10,7 @@ module settings_bus input wb_stb_i, input wb_we_i, output reg wb_ack_o, - output reg strobe, + output strobe, output reg [7:0] addr, output reg [31:0] data); @@ -19,18 +19,18 @@ module settings_bus always @(posedge wb_clk) if(wb_rst) begin - strobe <= 1'b0; + stb_int <= 1'b0; addr <= 8'd0; data <= 32'd0; end - else if(wb_we_i & wb_stb_i & ~wb_ack_o) + else if(wb_we_i & wb_stb_i) begin - strobe <= 1'b1; + stb_int <= 1'b1; addr <= wb_adr_i[9:2]; data <= wb_dat_i; end else - strobe <= 1'b0; + stb_int <= 1'b0; always @(posedge wb_clk) if(wb_rst) @@ -38,4 +38,11 @@ module settings_bus else wb_ack_o <= wb_stb_i & ~wb_ack_o; + always @(posedge wb_clk) + stb_int_d1 <= stb_int; + + //assign strobe = stb_int & ~stb_int_d1; + assign strobe = stb_int & wb_ack_o; + endmodule // settings_bus + -- cgit v1.2.3 From 4eef4015672ffafb56d66feb57848772f42b54e3 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 12 May 2010 16:10:08 -0700 Subject: move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing --- usrp2/top/u2_core/u2_core.v | 28 ++++++++++++++++------------ usrp2/top/u2_rev3/Makefile | 3 +++ 2 files changed, 19 insertions(+), 12 deletions(-) (limited to 'usrp2') diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 2302f59ee..b57e4f127 100644 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -154,9 +154,9 @@ module u2_core localparam SERDES_TX_FIFOSIZE = 9; localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; + wire [7:0] set_addr, set_addr_dsp; + wire [31:0] set_data, set_data_dsp; + wire set_stb, set_stb_dsp; wire ram_loader_done; wire ram_loader_rst, wb_rst, dsp_rst; @@ -359,7 +359,7 @@ module u2_core .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), .stream_clk(dsp_clk), .stream_rst(dsp_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), .status(status),.sys_int_o(buffer_int), .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), @@ -454,7 +454,7 @@ module u2_core udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), @@ -480,6 +480,10 @@ module u2_core assign s7_dat_i = 32'd0; + settings_bus_crossclock settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); + // Output control lines wire [7:0] clock_outs, serdes_outs, adc_outs; assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; @@ -600,7 +604,7 @@ module u2_core dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), .debug(debug_rx_dsp) ); @@ -609,7 +613,7 @@ module u2_core vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .overrun(overrun), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), @@ -619,7 +623,7 @@ module u2_core vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), .fifo_occupied(), .fifo_full(), .fifo_empty(), @@ -646,14 +650,14 @@ module u2_core vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), .debug(debug_vtd) ); vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time),.underrun(underrun), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), @@ -663,7 +667,7 @@ module u2_core dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .dac_a(dac_a),.dac_b(dac_b), .debug(debug_tx_dsp) ); @@ -720,7 +724,7 @@ module u2_core // VITA Timing time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit - (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); // ///////////////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 867fb5cab..af93700c5 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -70,6 +70,7 @@ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ control_lib/setting_reg.v \ control_lib/settings_bus.v \ +control_lib/settings_bus_crossclock.v \ control_lib/srl.v \ control_lib/system_control.v \ control_lib/wb_1master.v \ @@ -134,6 +135,8 @@ coregen/fifo_xlnx_64x36_2clk.v \ coregen/fifo_xlnx_64x36_2clk.xco \ coregen/fifo_xlnx_16x19_2clk.v \ coregen/fifo_xlnx_16x19_2clk.xco \ +coregen/fifo_xlnx_16x40_2clk.v \ +coregen/fifo_xlnx_16x40_2clk.xco \ extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ -- cgit v1.2.3 From ac32c1fef042a3041a37a8c68e505156cba31484 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 18 May 2010 00:05:54 -0700 Subject: ignores --- usrp2/top/u2_rev3/.gitignore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2') diff --git a/usrp2/top/u2_rev3/.gitignore b/usrp2/top/u2_rev3/.gitignore index 432f8fd58..f50a2b7e5 100644 --- a/usrp2/top/u2_rev3/.gitignore +++ b/usrp2/top/u2_rev3/.gitignore @@ -54,4 +54,4 @@ /*.rpt /*.cel /*.restore -/build +/build* -- cgit v1.2.3 From bc6968c3e33cd496c740bfd508c6d2e74d986019 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 19 May 2010 23:52:54 -0700 Subject: fix typo, no functionality difference --- usrp2/vrt/vita_tx_deframer.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2') diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 49428ead5..220d3b061 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -28,7 +28,7 @@ module vita_tx_deframer reg [3:0] vita_state; wire has_streamid, has_classid, has_secs, has_tics, has_trailer; - assign has_streamid = (data_i[31:28]==4'b001); + assign has_streamid = (data_i[31:28]==4'b0001); assign has_classid = data_i[27]; assign has_secs = ~(data_i[23:22]==2'b00); assign has_tics = ~(data_i[21:20]==2'b00); -- cgit v1.2.3 From b38d2424b1ac3242146fc9305d9e4ae80e21dede Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 19 May 2010 23:53:13 -0700 Subject: better test program for just the tx side --- usrp2/vrt/vita_tx_tb.v | 226 ++++++++++++++----------------------------------- 1 file changed, 63 insertions(+), 163 deletions(-) (limited to 'usrp2') diff --git a/usrp2/vrt/vita_tx_tb.v b/usrp2/vrt/vita_tx_tb.v index 90986a35f..0223d6850 100644 --- a/usrp2/vrt/vita_tx_tb.v +++ b/usrp2/vrt/vita_tx_tb.v @@ -5,7 +5,7 @@ module vita_tx_tb; localparam DECIM = 8'd4; localparam INTERP = 8'd4; - localparam MAXCHAN=4; + localparam MAXCHAN=1; localparam NUMCHAN=1; reg clk = 0; @@ -19,9 +19,9 @@ module vita_tx_tb; wire [(MAXCHAN*32)-1:0] sample, sample_tx; wire strobe, run; - wire [35:0] data_o; - wire src_rdy; - wire dst_rdy; + reg [35:0] data_o = 36'h0; + reg src_rdy = 0; + wire dst_rdy; wire [63:0] vita_time; @@ -32,42 +32,13 @@ module vita_tx_tb; wire [7:0] set_addr_dsp; wire [31:0] set_data_dsp; - /* - settings_bus_crossclock settings_bus_xclk_dsp - (.clk_i(clk), .rst_i(reset), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), - .clk_o(clk), .rst_o(reset), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - */ - wire sample_dst_rdy, sample_src_rdy; - //wire [99:0] sample_data_o; wire [64+4+(MAXCHAN*32)-1:0] sample_data_o, sample_data_tx; time_64bit #(.TICKS_PER_SEC(100000000), .BASE(0)) time_64bit (.clk(clk), .rst(reset), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .pps(0), .vita_time(vita_time)); - - rx_dsp_model rx_dsp_model - (.clk(clk), .reset(reset), .run(run), .decim(DECIM), .strobe(strobe), .sample(sample[31:0])); - - generate - if(MAXCHAN>1) - assign sample[(MAXCHAN*32)-1:32] = 0; - endgenerate - - vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control - (.clk(clk), .reset(reset), .clear(0), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .vita_time(vita_time), .overrun(overrun), - .sample_fifo_o(sample_data_o), .sample_fifo_dst_rdy_i(sample_dst_rdy), .sample_fifo_src_rdy_o(sample_src_rdy), - .sample(sample), .run(run), .strobe(strobe)); - - vita_rx_framer #(.BASE(0), .MAXCHAN(MAXCHAN)) vita_rx_framer - (.clk(clk), .reset(reset), .clear(0), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .data_o(data_o), .dst_rdy_i(dst_rdy), .src_rdy_o(src_rdy), - .sample_fifo_i(sample_data_o), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy), - .fifo_occupied(), .fifo_full(), .fifo_empty() ); wire [35:0] data_tx; wire src_rdy_tx, dst_rdy_tx; @@ -89,7 +60,7 @@ module vita_tx_tb; vita_tx_control #(.BASE(16), .WIDTH(MAXCHAN*32)) vita_tx_control (.clk(clk), .reset(reset), .clear(0), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .vita_time(vita_time-100), .underrun(underrun), + .vita_time(vita_time), .underrun(underrun), .sample_fifo_i(sample_data_tx), .sample_fifo_dst_rdy_o(sample_dst_rdy_tx), .sample_fifo_src_rdy_i(sample_src_rdy_tx), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx)); @@ -97,28 +68,20 @@ module vita_tx_tb; tx_dsp_model tx_dsp_model (.clk(clk), .reset(reset), .run(run_tx), .interp(INTERP), .strobe(strobe_tx), .sample(sample_tx[31:0] )); - always @(posedge clk) - if(src_rdy & dst_rdy) - begin - if(data_o[32] & ~data_o[33]) - begin - $display("RX-PKT-START %d",$time); - $display(" RX-PKT-DAT %x",data_o[31:0]); - end - else if(data_o[32] & data_o[33]) - begin - $display(" RX-PKT-DAT %x -- With ERR",data_o[31:0]); - $display("RX-PKT-ERR %d",$time); - end - else if(~data_o[32] & data_o[33]) - begin - $display(" RX-PKT-DAT %x",data_o[31:0]); - $display("RX-PKT-END %d",$time); - end - else - $display(" RX-PKT DAT %x",data_o[31:0]); - end - + task write_setting; + input [7:0] addr; + input [31:0] data; + begin + set_stb <= 0; + @(posedge clk); + set_addr <= addr; + set_data <= data; + set_stb <= 1; + @(posedge clk); + set_stb <= 0; + end + endtask // write_setting + initial begin @(negedge reset); @@ -129,124 +92,61 @@ module vita_tx_tb; write_setting(7,8); // Samples per VITA packet write_setting(8,NUMCHAN); // Samples per VITA packet #10000; + queue_vita_packets(32'h300, 106, 32'hF00D_1234, 32'h55AA_AA55); + //queue_vita_packets(32'h300, 6, 32'hF00D_1234, 32'h0); + queue_vita_packets(32'h600, 9, 32'h9876_ABCD, 32'h0); - queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet -/* - queue_rx_cmd(1,0,16,32'h0,32'h0); // send imm, 2 packets worth - queue_rx_cmd(1,0,7,32'h0,32'h0); // send imm, 1 short packet worth - queue_rx_cmd(1,0,9,32'h0,32'h0); // send imm, just longer than 1 packet - - queue_rx_cmd(1,1,16,32'h0,32'h0); // chained - queue_rx_cmd(0,0,8,32'h0,32'h0); // 2nd in chain - - queue_rx_cmd(1,1,17,32'h0,32'h0); // chained, odd length - queue_rx_cmd(0,0,9,32'h0,32'h0); // 2nd in chain, also odd length - - queue_rx_cmd(0,0,8,32'h0,32'h340); // send at, on time - queue_rx_cmd(0,0,8,32'h0,32'h100); // send at, but late - - queue_rx_cmd(1,1,8,32'h0,32'h0); // chained, but break chain - #100000; - $display("\nEnd chain with zero samples, shouldn't error\n"); - queue_rx_cmd(1,1,8,32'h0,32'h0); // chained - queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error - #100000; - - $display("\nEnd chain with zero samples on odd-length, shouldn't error\n"); - queue_rx_cmd(1,1,14,32'h0,32'h0); // chained - queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error - #100000; - $display("Should have gotten 14 samples and EOF by now\n"); - - queue_rx_cmd(1,1,9,32'h0,32'h0); // chained, but break chain, odd length - #100000; - //dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun - queue_rx_cmd(1,0,100,32'h0,32'h0); // long enough to fill the fifos - queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent - #100000; - //dst_rdy <= 1; // restart the reads so we can see what we got - #100000; - //dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun - queue_rx_cmd(1,1,100,32'h0,32'h0); // long enough to fill the fifos - //queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent - #100000; - @(posedge clk); - //dst_rdy <= 1; - */ - #100000 $finish; + #300000 $finish; end - task write_setting; - input [7:0] addr; - input [31:0] data; + task queue_vita_packets; + input [31:0] sendtime; + input [15:0] samples; + input [15:0] word; + input [31:0] trailer; + + reg [15:0] i; + begin - set_stb <= 0; @(posedge clk); - set_addr <= addr; - set_data <= data; - set_stb <= 1; + src_rdy <= 1; + data_o <= {4'b0001,4'h1,1'b0,|trailer,2'h3,8'hF0,(16'd5+samples+|trailer)}; // header @(posedge clk); - set_stb <= 0; - end - endtask // write_setting - - task queue_rx_cmd; - input send_imm; - input chain; - input [29:0] lines; - input [31:0] secs; - input [31:0] tics; - begin - write_setting(0,{send_imm,chain,lines}); - write_setting(1,secs); - write_setting(2,tics); + data_o <= {4'b0000,32'h0}; // streamid + @(posedge clk); + data_o <= {4'b0000,32'h0}; // SECS + @(posedge clk); + data_o <= {4'b0000,32'h0}; // TICS + @(posedge clk); + data_o <= {4'b0000,sendtime}; // TICS + @(posedge clk); + + for(i=0;i