From 2171188523f36a385c17c47aeb5c415085d163f4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 2 Feb 2011 16:22:29 -0800 Subject: put these files in the right place. newfifo is long gone. --- usrp2/control_lib/Makefile.srcs | 5 --- usrp2/control_lib/newfifo/fifo_pacer.v | 24 ---------- usrp2/control_lib/newfifo/packet32_tb.v | 27 ------------ usrp2/control_lib/newfifo/packet_generator.v | 59 ------------------------- usrp2/control_lib/newfifo/packet_generator32.v | 21 --------- usrp2/control_lib/newfifo/packet_tb.v | 29 ------------ usrp2/control_lib/newfifo/packet_verifier.v | 61 -------------------------- usrp2/control_lib/newfifo/packet_verifier32.v | 30 ------------- usrp2/fifo/Makefile.srcs | 5 +++ usrp2/fifo/fifo_pacer.v | 24 ++++++++++ usrp2/fifo/packet32_tb.v | 27 ++++++++++++ usrp2/fifo/packet_generator.v | 59 +++++++++++++++++++++++++ usrp2/fifo/packet_generator32.v | 21 +++++++++ usrp2/fifo/packet_tb.v | 29 ++++++++++++ usrp2/fifo/packet_verifier.v | 61 ++++++++++++++++++++++++++ usrp2/fifo/packet_verifier32.v | 30 +++++++++++++ 16 files changed, 256 insertions(+), 256 deletions(-) delete mode 100644 usrp2/control_lib/newfifo/fifo_pacer.v delete mode 100644 usrp2/control_lib/newfifo/packet32_tb.v delete mode 100644 usrp2/control_lib/newfifo/packet_generator.v delete mode 100644 usrp2/control_lib/newfifo/packet_generator32.v delete mode 100644 usrp2/control_lib/newfifo/packet_tb.v delete mode 100644 usrp2/control_lib/newfifo/packet_verifier.v delete mode 100644 usrp2/control_lib/newfifo/packet_verifier32.v create mode 100644 usrp2/fifo/fifo_pacer.v create mode 100644 usrp2/fifo/packet32_tb.v create mode 100644 usrp2/fifo/packet_generator.v create mode 100644 usrp2/fifo/packet_generator32.v create mode 100644 usrp2/fifo/packet_tb.v create mode 100644 usrp2/fifo/packet_verifier.v create mode 100644 usrp2/fifo/packet_verifier32.v (limited to 'usrp2') diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs index 5ae185ee8..751b40828 100644 --- a/usrp2/control_lib/Makefile.srcs +++ b/usrp2/control_lib/Makefile.srcs @@ -50,9 +50,4 @@ bootram.v \ nsgpio16LE.v \ settings_bus_16LE.v \ atr_controller16.v \ -newfifo/fifo_pacer.v \ -newfifo/packet_generator32.v \ -newfifo/packet_generator.v \ -newfifo/packet_verifier32.v \ -newfifo/packet_verifier.v \ )) diff --git a/usrp2/control_lib/newfifo/fifo_pacer.v b/usrp2/control_lib/newfifo/fifo_pacer.v deleted file mode 100644 index 1bf03ab6e..000000000 --- a/usrp2/control_lib/newfifo/fifo_pacer.v +++ /dev/null @@ -1,24 +0,0 @@ - - -module fifo_pacer - (input clk, - input reset, - input [7:0] rate, - input enable, - input src1_rdy_i, output dst1_rdy_o, - output src2_rdy_o, input dst2_rdy_i, - output underrun, overrun); - - wire strobe; - - cic_strober strober (.clock(clk), .reset(reset), .enable(enable), - .rate(rate), .strobe_fast(1), .strobe_slow(strobe)); - - wire all_ready = src1_rdy_i & dst2_rdy_i; - assign dst1_rdy_o = all_ready & strobe; - assign src2_rdy_o = dst1_rdy_o; - - assign underrun = strobe & ~src1_rdy_i; - assign overrun = strobe & ~dst2_rdy_i; - -endmodule // fifo_pacer diff --git a/usrp2/control_lib/newfifo/packet32_tb.v b/usrp2/control_lib/newfifo/packet32_tb.v deleted file mode 100644 index 82bb09c29..000000000 --- a/usrp2/control_lib/newfifo/packet32_tb.v +++ /dev/null @@ -1,27 +0,0 @@ - - -module packet32_tb(); - - wire [35:0] data; - wire src_rdy, dst_rdy; - - wire clear = 0; - reg clk = 0; - reg reset = 1; - - always #10 clk <= ~clk; - initial #1000 reset <= 0; - - initial $dumpfile("packet32_tb.vcd"); - initial $dumpvars(0,packet32_tb); - - wire [31:0] total, crc_err, seq_err, len_err; - - packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear), - .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); - - packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear), - .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), - .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); - -endmodule // packet32_tb diff --git a/usrp2/control_lib/newfifo/packet_generator.v b/usrp2/control_lib/newfifo/packet_generator.v deleted file mode 100644 index 6e8b45ccd..000000000 --- a/usrp2/control_lib/newfifo/packet_generator.v +++ /dev/null @@ -1,59 +0,0 @@ - - -module packet_generator - (input clk, input reset, input clear, - output reg [7:0] data_o, output sof_o, output eof_o, - output src_rdy_o, input dst_rdy_i); - - localparam len = 32'd2000; - - reg [31:0] state; - reg [31:0] seq; - wire [31:0] crc_out; - wire calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF); - - - always @(posedge clk) - if(reset | clear) - seq <= 0; - else - if(eof_o & src_rdy_o & dst_rdy_i) - seq <= seq + 1; - - always @(posedge clk) - if(reset | clear) - state <= 0; - else - if(src_rdy_o & dst_rdy_i) - if(state == (len - 1)) - state <= 32'hFFFF_FFFC; - else - state <= state + 1; - - always @* - case(state) - 0 : data_o <= len[7:0]; - 1 : data_o <= len[15:8]; - 2 : data_o <= len[23:16]; - 3 : data_o <= len[31:24]; - 4 : data_o <= seq[7:0]; - 5 : data_o <= seq[15:8]; - 6 : data_o <= seq[23:16]; - 7 : data_o <= seq[31:24]; - 32'hFFFF_FFFC : data_o <= crc_out[31:24]; - 32'hFFFF_FFFD : data_o <= crc_out[23:16]; - 32'hFFFF_FFFE : data_o <= crc_out[15:8]; - 32'hFFFF_FFFF : data_o <= crc_out[7:0]; - default : data_o <= state[7:0]; - endcase // case (state) - - assign src_rdy_o = 1; - assign sof_o = (state == 0); - assign eof_o = (state == 32'hFFFF_FFFF); - - wire clear_crc = eof_o & src_rdy_o & dst_rdy_i; - - crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), - .calc(calc_crc), .crc_out(crc_out), .match()); - -endmodule // packet_generator diff --git a/usrp2/control_lib/newfifo/packet_generator32.v b/usrp2/control_lib/newfifo/packet_generator32.v deleted file mode 100644 index 6f8004964..000000000 --- a/usrp2/control_lib/newfifo/packet_generator32.v +++ /dev/null @@ -1,21 +0,0 @@ - - -module packet_generator32 - (input clk, input reset, input clear, - output [35:0] data_o, output src_rdy_o, input dst_rdy_i); - - wire [7:0] ll_data; - wire ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n; - - packet_generator pkt_gen - (.clk(clk), .reset(reset), .clear(clear), - .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof), - .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n)); - - ll8_to_fifo36 ll8_to_f36 - (.clk(clk), .reset(reset), .clear(clear), - .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof), - .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n), - .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i)); - -endmodule // packet_generator32 diff --git a/usrp2/control_lib/newfifo/packet_tb.v b/usrp2/control_lib/newfifo/packet_tb.v deleted file mode 100644 index 3c423d2ba..000000000 --- a/usrp2/control_lib/newfifo/packet_tb.v +++ /dev/null @@ -1,29 +0,0 @@ - - -module packet_tb(); - - wire [7:0] data; - wire sof, eof, src_rdy, dst_rdy; - - wire clear = 0; - reg clk = 0; - reg reset = 1; - - always #10 clk <= ~clk; - initial #1000 reset <= 0; - - initial $dumpfile("packet_tb.vcd"); - initial $dumpvars(0,packet_tb); - - wire [31:0] total, crc_err, seq_err, len_err; - - packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear), - .data_o(data), .sof_o(sof), .eof_o(eof), - .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); - - packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear), - .data_i(data), .sof_i(sof), .eof_i(eof), - .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), - .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); - -endmodule // packet_tb diff --git a/usrp2/control_lib/newfifo/packet_verifier.v b/usrp2/control_lib/newfifo/packet_verifier.v deleted file mode 100644 index b49ad1bbb..000000000 --- a/usrp2/control_lib/newfifo/packet_verifier.v +++ /dev/null @@ -1,61 +0,0 @@ - - -// Packet format -- -// Line 1 -- Length, 32 bits -// Line 2 -- Sequence number, 32 bits -// Last line -- CRC, 32 bits - -module packet_verifier - (input clk, input reset, input clear, - input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o, - - output reg [31:0] total, - output reg [31:0] crc_err, - output reg [31:0] seq_err, - output reg [31:0] len_err); - - reg [31:0] seq_num; - reg [31:0] length; - wire first_byte, last_byte; - reg second_byte, last_byte_d1; - - wire calc_crc = src_rdy_i & dst_rdy_o; - - crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), - .calc(calc_crc), .crc_out(), .match(match_crc)); - - assign first_byte = src_rdy_i & dst_rdy_o & sof_i; - assign last_byte = src_rdy_i & dst_rdy_o & eof_i; - assign dst_rdy_o = ~last_byte_d1; - - // stubs for now - wire match_seq = 1; - wire match_len = 1; - - always @(posedge clk) - if(reset | clear) - last_byte_d1 <= 0; - else - last_byte_d1 <= last_byte; - - always @(posedge clk) - if(reset | clear) - begin - total <= 0; - crc_err <= 0; - seq_err <= 0; - len_err <= 0; - end - else - if(last_byte_d1) - begin - total <= total + 1; - if(~match_crc) - crc_err <= crc_err + 1; - else if(~match_seq) - seq_err <= seq_err + 1; - else if(~match_len) - seq_err <= len_err + 1; - end - -endmodule // packet_verifier diff --git a/usrp2/control_lib/newfifo/packet_verifier32.v b/usrp2/control_lib/newfifo/packet_verifier32.v deleted file mode 100644 index 06a13d242..000000000 --- a/usrp2/control_lib/newfifo/packet_verifier32.v +++ /dev/null @@ -1,30 +0,0 @@ - - -module packet_verifier32 - (input clk, input reset, input clear, - input [35:0] data_i, input src_rdy_i, output dst_rdy_o, - output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err); - - wire [7:0] ll_data; - wire ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy; - wire [35:0] data_int; - wire src_rdy_int, dst_rdy_int; - - fifo_short #(.WIDTH(36)) fifo_short - (.clk(clk), .reset(reset), .clear(clear), - .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); - - fifo36_to_ll8 f36_to_ll8 - (.clk(clk), .reset(reset), .clear(clear), - .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), - .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n), - .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy)); - - packet_verifier pkt_ver - (.clk(clk), .reset(reset), .clear(clear), - .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n), - .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy), - .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); - -endmodule // packet_verifier32 diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs index f0b5b7bae..c1287cd5c 100644 --- a/usrp2/fifo/Makefile.srcs +++ b/usrp2/fifo/Makefile.srcs @@ -28,4 +28,9 @@ fifo36_demux.v \ packet_router.v \ splitter36.v \ valve36.v \ +fifo_pacer.v \ +packet_generator32.v \ +packet_generator.v \ +packet_verifier32.v \ +packet_verifier.v \ )) diff --git a/usrp2/fifo/fifo_pacer.v b/usrp2/fifo/fifo_pacer.v new file mode 100644 index 000000000..1bf03ab6e --- /dev/null +++ b/usrp2/fifo/fifo_pacer.v @@ -0,0 +1,24 @@ + + +module fifo_pacer + (input clk, + input reset, + input [7:0] rate, + input enable, + input src1_rdy_i, output dst1_rdy_o, + output src2_rdy_o, input dst2_rdy_i, + output underrun, overrun); + + wire strobe; + + cic_strober strober (.clock(clk), .reset(reset), .enable(enable), + .rate(rate), .strobe_fast(1), .strobe_slow(strobe)); + + wire all_ready = src1_rdy_i & dst2_rdy_i; + assign dst1_rdy_o = all_ready & strobe; + assign src2_rdy_o = dst1_rdy_o; + + assign underrun = strobe & ~src1_rdy_i; + assign overrun = strobe & ~dst2_rdy_i; + +endmodule // fifo_pacer diff --git a/usrp2/fifo/packet32_tb.v b/usrp2/fifo/packet32_tb.v new file mode 100644 index 000000000..82bb09c29 --- /dev/null +++ b/usrp2/fifo/packet32_tb.v @@ -0,0 +1,27 @@ + + +module packet32_tb(); + + wire [35:0] data; + wire src_rdy, dst_rdy; + + wire clear = 0; + reg clk = 0; + reg reset = 1; + + always #10 clk <= ~clk; + initial #1000 reset <= 0; + + initial $dumpfile("packet32_tb.vcd"); + initial $dumpvars(0,packet32_tb); + + wire [31:0] total, crc_err, seq_err, len_err; + + packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear), + .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear), + .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet32_tb diff --git a/usrp2/fifo/packet_generator.v b/usrp2/fifo/packet_generator.v new file mode 100644 index 000000000..6e8b45ccd --- /dev/null +++ b/usrp2/fifo/packet_generator.v @@ -0,0 +1,59 @@ + + +module packet_generator + (input clk, input reset, input clear, + output reg [7:0] data_o, output sof_o, output eof_o, + output src_rdy_o, input dst_rdy_i); + + localparam len = 32'd2000; + + reg [31:0] state; + reg [31:0] seq; + wire [31:0] crc_out; + wire calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF); + + + always @(posedge clk) + if(reset | clear) + seq <= 0; + else + if(eof_o & src_rdy_o & dst_rdy_i) + seq <= seq + 1; + + always @(posedge clk) + if(reset | clear) + state <= 0; + else + if(src_rdy_o & dst_rdy_i) + if(state == (len - 1)) + state <= 32'hFFFF_FFFC; + else + state <= state + 1; + + always @* + case(state) + 0 : data_o <= len[7:0]; + 1 : data_o <= len[15:8]; + 2 : data_o <= len[23:16]; + 3 : data_o <= len[31:24]; + 4 : data_o <= seq[7:0]; + 5 : data_o <= seq[15:8]; + 6 : data_o <= seq[23:16]; + 7 : data_o <= seq[31:24]; + 32'hFFFF_FFFC : data_o <= crc_out[31:24]; + 32'hFFFF_FFFD : data_o <= crc_out[23:16]; + 32'hFFFF_FFFE : data_o <= crc_out[15:8]; + 32'hFFFF_FFFF : data_o <= crc_out[7:0]; + default : data_o <= state[7:0]; + endcase // case (state) + + assign src_rdy_o = 1; + assign sof_o = (state == 0); + assign eof_o = (state == 32'hFFFF_FFFF); + + wire clear_crc = eof_o & src_rdy_o & dst_rdy_i; + + crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), + .calc(calc_crc), .crc_out(crc_out), .match()); + +endmodule // packet_generator diff --git a/usrp2/fifo/packet_generator32.v b/usrp2/fifo/packet_generator32.v new file mode 100644 index 000000000..6f8004964 --- /dev/null +++ b/usrp2/fifo/packet_generator32.v @@ -0,0 +1,21 @@ + + +module packet_generator32 + (input clk, input reset, input clear, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + wire [7:0] ll_data; + wire ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n; + + packet_generator pkt_gen + (.clk(clk), .reset(reset), .clear(clear), + .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof), + .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n)); + + ll8_to_fifo36 ll8_to_f36 + (.clk(clk), .reset(reset), .clear(clear), + .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof), + .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n), + .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i)); + +endmodule // packet_generator32 diff --git a/usrp2/fifo/packet_tb.v b/usrp2/fifo/packet_tb.v new file mode 100644 index 000000000..3c423d2ba --- /dev/null +++ b/usrp2/fifo/packet_tb.v @@ -0,0 +1,29 @@ + + +module packet_tb(); + + wire [7:0] data; + wire sof, eof, src_rdy, dst_rdy; + + wire clear = 0; + reg clk = 0; + reg reset = 1; + + always #10 clk <= ~clk; + initial #1000 reset <= 0; + + initial $dumpfile("packet_tb.vcd"); + initial $dumpvars(0,packet_tb); + + wire [31:0] total, crc_err, seq_err, len_err; + + packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear), + .data_o(data), .sof_o(sof), .eof_o(eof), + .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear), + .data_i(data), .sof_i(sof), .eof_i(eof), + .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet_tb diff --git a/usrp2/fifo/packet_verifier.v b/usrp2/fifo/packet_verifier.v new file mode 100644 index 000000000..b49ad1bbb --- /dev/null +++ b/usrp2/fifo/packet_verifier.v @@ -0,0 +1,61 @@ + + +// Packet format -- +// Line 1 -- Length, 32 bits +// Line 2 -- Sequence number, 32 bits +// Last line -- CRC, 32 bits + +module packet_verifier + (input clk, input reset, input clear, + input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o, + + output reg [31:0] total, + output reg [31:0] crc_err, + output reg [31:0] seq_err, + output reg [31:0] len_err); + + reg [31:0] seq_num; + reg [31:0] length; + wire first_byte, last_byte; + reg second_byte, last_byte_d1; + + wire calc_crc = src_rdy_i & dst_rdy_o; + + crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), + .calc(calc_crc), .crc_out(), .match(match_crc)); + + assign first_byte = src_rdy_i & dst_rdy_o & sof_i; + assign last_byte = src_rdy_i & dst_rdy_o & eof_i; + assign dst_rdy_o = ~last_byte_d1; + + // stubs for now + wire match_seq = 1; + wire match_len = 1; + + always @(posedge clk) + if(reset | clear) + last_byte_d1 <= 0; + else + last_byte_d1 <= last_byte; + + always @(posedge clk) + if(reset | clear) + begin + total <= 0; + crc_err <= 0; + seq_err <= 0; + len_err <= 0; + end + else + if(last_byte_d1) + begin + total <= total + 1; + if(~match_crc) + crc_err <= crc_err + 1; + else if(~match_seq) + seq_err <= seq_err + 1; + else if(~match_len) + seq_err <= len_err + 1; + end + +endmodule // packet_verifier diff --git a/usrp2/fifo/packet_verifier32.v b/usrp2/fifo/packet_verifier32.v new file mode 100644 index 000000000..06a13d242 --- /dev/null +++ b/usrp2/fifo/packet_verifier32.v @@ -0,0 +1,30 @@ + + +module packet_verifier32 + (input clk, input reset, input clear, + input [35:0] data_i, input src_rdy_i, output dst_rdy_o, + output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err); + + wire [7:0] ll_data; + wire ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy; + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + + fifo_short #(.WIDTH(36)) fifo_short + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); + + fifo36_to_ll8 f36_to_ll8 + (.clk(clk), .reset(reset), .clear(clear), + .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), + .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n), + .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy)); + + packet_verifier pkt_ver + (.clk(clk), .reset(reset), .clear(clear), + .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n), + .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet_verifier32 -- cgit v1.2.3 From 4c377e12d56be4afa78b0f83dd8546b59ec837f2 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 10 Feb 2011 15:47:57 -0500 Subject: Fix endianess for packet length and sequence number for e100 timed image. --- usrp2/fifo/packet_generator.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'usrp2') diff --git a/usrp2/fifo/packet_generator.v b/usrp2/fifo/packet_generator.v index 6e8b45ccd..a751fdfb1 100644 --- a/usrp2/fifo/packet_generator.v +++ b/usrp2/fifo/packet_generator.v @@ -32,14 +32,14 @@ module packet_generator always @* case(state) - 0 : data_o <= len[7:0]; - 1 : data_o <= len[15:8]; - 2 : data_o <= len[23:16]; - 3 : data_o <= len[31:24]; - 4 : data_o <= seq[7:0]; - 5 : data_o <= seq[15:8]; - 6 : data_o <= seq[23:16]; - 7 : data_o <= seq[31:24]; + 0 : data_o <= len[31:24]; + 1 : data_o <= len[23:16]; + 2 : data_o <= len[15:8]; + 3 : data_o <= len[7:0]; + 4 : data_o <= seq[31:24]; + 5 : data_o <= seq[23:16]; + 6 : data_o <= seq[15:8]; + 7 : data_o <= seq[7:0]; 32'hFFFF_FFFC : data_o <= crc_out[31:24]; 32'hFFFF_FFFD : data_o <= crc_out[23:16]; 32'hFFFF_FFFE : data_o <= crc_out[15:8]; -- cgit v1.2.3 From 57f956af2f9cc3463970e8d47c2f59ec549accbf Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 16 Feb 2011 17:04:30 -0800 Subject: e100: integrate loopback and timed testing into main image --- usrp2/fifo/packet_generator.v | 20 ++++++++- usrp2/fifo/packet_generator32.v | 2 + usrp2/fifo/packet_verifier.v | 2 +- usrp2/gpmc/gpmc_async.v | 94 ++++++++++++++++++++++++++++++++++++++--- usrp2/top/u1e/u1e_core.v | 75 +------------------------------- 5 files changed, 112 insertions(+), 81 deletions(-) (limited to 'usrp2') diff --git a/usrp2/fifo/packet_generator.v b/usrp2/fifo/packet_generator.v index a751fdfb1..bbcab6db2 100644 --- a/usrp2/fifo/packet_generator.v +++ b/usrp2/fifo/packet_generator.v @@ -2,7 +2,8 @@ module packet_generator (input clk, input reset, input clear, - output reg [7:0] data_o, output sof_o, output eof_o, + output reg [7:0] data_o, output sof_o, output eof_o, + input [127:0] header, output src_rdy_o, input dst_rdy_i); localparam len = 32'd2000; @@ -40,6 +41,23 @@ module packet_generator 5 : data_o <= seq[23:16]; 6 : data_o <= seq[15:8]; 7 : data_o <= seq[7:0]; + 8 : data_o <= header[7:0]; + 9 : data_o <= header[15:8]; + 10 : data_o <= header[23:16]; + 11 : data_o <= header[31:24]; + 12 : data_o <= header[39:32]; + 13 : data_o <= header[47:40]; + 14 : data_o <= header[55:48]; + 15 : data_o <= header[63:56]; + 16 : data_o <= header[71:64]; + 17 : data_o <= header[79:72]; + 18 : data_o <= header[87:80]; + 19 : data_o <= header[95:88]; + 20 : data_o <= header[103:96]; + 21 : data_o <= header[111:104]; + 22 : data_o <= header[119:112]; + 23 : data_o <= header[127:120]; + 32'hFFFF_FFFC : data_o <= crc_out[31:24]; 32'hFFFF_FFFD : data_o <= crc_out[23:16]; 32'hFFFF_FFFE : data_o <= crc_out[15:8]; diff --git a/usrp2/fifo/packet_generator32.v b/usrp2/fifo/packet_generator32.v index 6f8004964..1dc57191d 100644 --- a/usrp2/fifo/packet_generator32.v +++ b/usrp2/fifo/packet_generator32.v @@ -2,6 +2,7 @@ module packet_generator32 (input clk, input reset, input clear, + input [127:0] header, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); wire [7:0] ll_data; @@ -10,6 +11,7 @@ module packet_generator32 packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear), .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof), + .header(header), .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n)); ll8_to_fifo36 ll8_to_f36 diff --git a/usrp2/fifo/packet_verifier.v b/usrp2/fifo/packet_verifier.v index b49ad1bbb..21a4c136e 100644 --- a/usrp2/fifo/packet_verifier.v +++ b/usrp2/fifo/packet_verifier.v @@ -18,7 +18,7 @@ module packet_verifier reg [31:0] length; wire first_byte, last_byte; reg second_byte, last_byte_d1; - + wire match_crc; wire calc_crc = src_rdy_i & dst_rdy_o; crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 23bad56ae..b2c91dfbc 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -1,7 +1,9 @@ ////////////////////////////////////////////////////////////////////////////////// module gpmc_async - #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11) + #(parameter TXFIFOSIZE = 11, + parameter RXFIFOSIZE = 11, + parameter BUSDEBUG = 1) (// GPMC signals input arst, input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, @@ -70,9 +72,9 @@ module gpmc_async .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 - (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), - .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); + .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy)); // //////////////////////////////////////////// // RX Data Path @@ -85,8 +87,8 @@ module gpmc_async wire dummy; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 - (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), - .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE @@ -126,5 +128,87 @@ module gpmc_async .wb_ack_i(wb_ack_i) ); assign debug = pkt_count; + + // //////////////////////////////////////////// + // Test support, traffic generator, loopback, etc. + + // RX side muxes test data into the same stream + wire [35:0] timedrx_data, loopbackrx_data, testrx_data, rx_data; + wire [35:0] timedtx_data, loopbacktx_data, testtx_data, tx_data; + wire timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy, + testrx_src_rdy, testrx_dst_rdy, rx_src_rdy, rx_dst_rdy; + wire timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy, + testtx_src_rdy, testtx_dst_rdy, tx_src_rdy, tx_dst_rdy; + wire timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int; + + wire [31:0] total, crc_err, seq_err, len_err; + wire [7:0] rx_rate, tx_rate; + wire rx_enable, tx_enable; + wire underrun, overrun; + wire sel_testtx, sel_loopbacktx; + + fifo36_mux rx_test_mux_lvl_1 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data0_i(timedrx_data), .src0_rdy_i(timedrx_src_rdy), .dst0_rdy_o(timedrx_dst_rdy), + .data1_i(loopbackrx_data), .src1_rdy_i(loopbackrx_src_rdy), .dst1_rdy_o(loopbackrx_dst_rdy), + .data_o(testrx_data), .src_rdy_o(testrx_src_rdy), .dst_rdy_i(testrx_dst_rdy)); + + fifo36_mux rx_test_mux_lvl_2 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data0_i(testrx_data), .src0_rdy_i(testrx_src_rdy), .dst0_rdy_o(testrx_dst_rdy), + .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + fifo_short #(.WIDTH(36)) loopback_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx), + .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy), + .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy)); + // Crossbar used as a demux for switching TX stream to main DSP or to test logic + crossbar36 tx_crossbar_lvl_1 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .cross(sel_testtx), + .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy), + .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input + .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i), + .data1_o(testtx_data), .src1_rdy_o(testtx_src_rdy), .dst1_rdy_i(testtx_dst_rdy) ); + + crossbar36 tx_crossbar_lvl_2 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .cross(sel_loopbacktx), + .data0_i(testtx_data), .src0_rdy_i(testtx_src_rdy), .dst0_rdy_o(testtx_dst_rdy), + .data1_i(testtx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input + .data0_o(timedtx_data), .src0_rdy_o(timedtx_src_rdy), .dst0_rdy_i(timedtx_dst_rdy), + .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) ); + + // Fixed rate TX traffic consumer + fifo_pacer tx_pacer + (.clk(fifo_clk), .reset(fifo_rst), .rate(tx_rate), .enable(tx_enable), + .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy), + .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int), + .underrun(underrun), .overrun()); + + packet_verifier32 pktver32 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .data_i(timedtx_data), .src_rdy_i(timedtx_src_rdy_int), .dst_rdy_o(timedtx_dst_rdy_int), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + + // Fixed rate RX traffic generator + packet_generator32 pktgen32 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .header({len_err,seq_err,crc_err,total}), + .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int)); + + fifo_pacer rx_pacer + (.clk(fifo_clk), .reset(fifo_rst), .rate(rx_rate), .enable(rx_enable), + .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int), + .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy), + .underrun(), .overrun(overrun)); + + // FIXME -- hook up crossbar controls + // FIXME -- collect error stats + // FIXME -- set rates and enables on pacers + // FIXME -- make sure packet completes before we shutoff + // FIXME -- handle overrun and underrun + endmodule // gpmc_async diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 7d5924bea..4f5a3e112 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -1,9 +1,5 @@ -//`define LOOPBACK 1 -//`define TIMED 1 -`define DSP 1 - module u1e_core (input clk_fpga, input rst_fpga, output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, @@ -117,56 +113,6 @@ module u1e_core wire rx_eof = rx_data[33]; wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; -`ifdef LOOPBACK - wire [7:0] WHOAMI = 1; - - fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo - (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx), - .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), - .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); - - assign tx_underrun = 0; - assign rx_overrun = 0; - - wire run_tx, run_rx, strobe_tx, strobe_rx; -`endif // LOOPBACK - -`ifdef TIMED - wire [7:0] WHOAMI = 2; - - // TX side - wire tx_enable; - - fifo_pacer tx_pacer - (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable), - .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy), - .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int), - .underrun(tx_underrun), .overrun()); - - packet_verifier32 pktver32 - (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), - .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int), - .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); - - // RX side - wire rx_enable; - - packet_generator32 pktgen32 - (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), - .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int)); - - fifo_pacer rx_pacer - (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable), - .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int), - .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy), - .underrun(), .overrun(rx_overrun)); - - wire run_tx, run_rx, strobe_tx, strobe_rx; -`endif // `ifdef TIMED - -`ifdef DSP - wire [7:0] WHOAMI = 0; - wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; // ///////////////////////////////////////////////////////////////////////// @@ -231,23 +177,6 @@ module u1e_core assign tx_i = tx_i_int[15:2]; assign tx_q = tx_q_int[15:2]; -`else // !`ifdef DSP - // Dummy DSP signal generator for test purposes - wire [23:0] tx_i_int, tx_q_int; - wire [23:0] freq = {reg_test,8'd0}; - reg [23:0] phase; - - always @(posedge wb_clk) - phase <= phase + freq; - - cordic_z24 #(.bitwidth(24)) tx_cordic - (.clock(wb_clk), .reset(wb_rst), .enable(1), - .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo()); - - assign tx_i = tx_i_int[23:10]; - assign tx_q = tx_q_int[23:10]; -`endif // !`ifdef DSP - // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, @@ -320,7 +249,6 @@ module u1e_core // Slave 0, Misc LEDs, Switches, controls localparam REG_LEDS = 7'd0; // out - localparam REG_SWITCHES = 7'd2; // in localparam REG_CGEN_CTRL = 7'd4; // out localparam REG_CGEN_ST = 7'd6; // in localparam REG_TEST = 7'd8; // out @@ -361,12 +289,11 @@ module u1e_core assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : - (s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } : (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : - (s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } : + (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; -- cgit v1.2.3 From 74346c49eda60ed5916908efb8d245b7e8852f6f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 16 Feb 2011 17:58:04 -0800 Subject: hook up under/overruns for debug purposes --- usrp2/gpmc/gpmc_async.v | 10 +++++----- usrp2/top/u1e/u1e_core.v | 10 +++++++--- 2 files changed, 12 insertions(+), 8 deletions(-) (limited to 'usrp2') diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index b2c91dfbc..38bfd3e25 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -23,7 +23,8 @@ module gpmc_async input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, input [15:0] tx_frame_len, output [15:0] rx_frame_len, - + + output tx_underrun, output rx_overrun, output [31:0] debug ); @@ -144,7 +145,6 @@ module gpmc_async wire [31:0] total, crc_err, seq_err, len_err; wire [7:0] rx_rate, tx_rate; wire rx_enable, tx_enable; - wire underrun, overrun; wire sel_testtx, sel_loopbacktx; fifo36_mux rx_test_mux_lvl_1 @@ -186,7 +186,7 @@ module gpmc_async (.clk(fifo_clk), .reset(fifo_rst), .rate(tx_rate), .enable(tx_enable), .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy), .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int), - .underrun(underrun), .overrun()); + .underrun(tx_underrun), .overrun()); packet_verifier32 pktver32 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), @@ -203,10 +203,10 @@ module gpmc_async (.clk(fifo_clk), .reset(fifo_rst), .rate(rx_rate), .enable(rx_enable), .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int), .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy), - .underrun(), .overrun(overrun)); + .underrun(), .overrun(rx_overrun)); // FIXME -- hook up crossbar controls - // FIXME -- collect error stats + // // FIXME -- collect error stats // FIXME -- set rates and enables on pacers // FIXME -- make sure packet completes before we shutoff // FIXME -- handle overrun and underrun diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 4f5a3e112..c0e92ec6c 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -50,7 +50,10 @@ module u1e_core wire set_stb; wire [31:0] debug_vt; - + wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; + assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; + assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; + setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(global_reset)); @@ -107,6 +110,7 @@ module u1e_core .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), + .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), .debug(debug_gpmc)); wire rx_sof = rx_data[32]; @@ -135,7 +139,7 @@ module u1e_core vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(rx_overrun), + .vita_time(vita_time), .overrun(rx_overrun_dsp), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), .debug_rx(vrc_debug)); @@ -171,7 +175,7 @@ module u1e_core .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(tx_i_int),.dac_b(tx_q_int), - .underrun(underrun), .run(run_tx), + .underrun(tx_underrun_dsp), .run(run_tx), .debug(debug_vt)); assign tx_i = tx_i_int[15:2]; -- cgit v1.2.3 From 3660330fae97026a74cd5d396a04040ab324ca09 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 16 Feb 2011 18:22:49 -0800 Subject: move declarations to before use --- usrp2/gpmc/gpmc_async.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'usrp2') diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 38bfd3e25..895b68a9f 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -52,8 +52,8 @@ module gpmc_async wire [17:0] tx18_data, tx18b_data; wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; wire [15:0] tx_fifo_space; - wire [35:0] tx36_data; - wire tx36_src_rdy, tx36_dst_rdy; + wire [35:0] tx36_data, tx_data; + wire tx36_src_rdy, tx36_dst_rdy, tx_src_rdy, tx_dst_rdy; gpmc_to_fifo_async gpmc_to_fifo_async (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), @@ -83,8 +83,8 @@ module gpmc_async wire [17:0] rx18_data, rx18b_data; wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; wire [15:0] rx_fifo_space; - wire [35:0] rx36_data; - wire rx36_src_rdy, rx36_dst_rdy; + wire [35:0] rx36_data, rx_data; + wire rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy; wire dummy; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 @@ -134,12 +134,12 @@ module gpmc_async // Test support, traffic generator, loopback, etc. // RX side muxes test data into the same stream - wire [35:0] timedrx_data, loopbackrx_data, testrx_data, rx_data; - wire [35:0] timedtx_data, loopbacktx_data, testtx_data, tx_data; + wire [35:0] timedrx_data, loopbackrx_data, testrx_data; + wire [35:0] timedtx_data, loopbacktx_data, testtx_data; wire timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy, - testrx_src_rdy, testrx_dst_rdy, rx_src_rdy, rx_dst_rdy; + testrx_src_rdy, testrx_dst_rdy; wire timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy, - testtx_src_rdy, testtx_dst_rdy, tx_src_rdy, tx_dst_rdy; + testtx_src_rdy, testtx_dst_rdy; wire timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int; wire [31:0] total, crc_err, seq_err, len_err; -- cgit v1.2.3 From ee50f438752a4beb780c3340026e2f29c1c32a3e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 17 Feb 2011 16:33:41 -0800 Subject: u1e: hook up tester controls --- usrp2/gpmc/gpmc_async.v | 12 +++++++----- usrp2/top/u1e/u1e_core.v | 10 ++++++---- 2 files changed, 13 insertions(+), 9 deletions(-) (limited to 'usrp2') diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 895b68a9f..7d38c66cb 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -25,6 +25,7 @@ module gpmc_async input [15:0] tx_frame_len, output [15:0] rx_frame_len, output tx_underrun, output rx_overrun, + input [7:0] test_rate, input [3:0] test_ctrl, output [31:0] debug ); @@ -143,9 +144,10 @@ module gpmc_async wire timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int; wire [31:0] total, crc_err, seq_err, len_err; - wire [7:0] rx_rate, tx_rate; - wire rx_enable, tx_enable; - wire sel_testtx, sel_loopbacktx; + wire sel_testtx = test_ctrl[0]; + wire sel_loopbacktx = test_ctrl[1]; + wire pkt_src_enable = test_ctrl[2]; + wire pkt_sink_enable = test_ctrl[3]; fifo36_mux rx_test_mux_lvl_1 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), @@ -183,7 +185,7 @@ module gpmc_async // Fixed rate TX traffic consumer fifo_pacer tx_pacer - (.clk(fifo_clk), .reset(fifo_rst), .rate(tx_rate), .enable(tx_enable), + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_sink_enable), .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy), .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int), .underrun(tx_underrun), .overrun()); @@ -200,7 +202,7 @@ module gpmc_async .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int)); fifo_pacer rx_pacer - (.clk(fifo_clk), .reset(fifo_rst), .rate(rx_rate), .enable(rx_enable), + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_src_enable), .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int), .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy), .underrun(), .overrun(rx_overrun)); diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index c0e92ec6c..174a2a3f8 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -44,6 +44,8 @@ module u1e_core wire pps_int; wire [63:0] vita_time, vita_time_pps; reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + wire [7:0] test_rate; + wire [3:0] test_ctrl; wire [7:0] set_addr; wire [31:0] set_data; @@ -78,7 +80,6 @@ module u1e_core tx_err_src_rdy, tx_err_dst_rdy; reg [15:0] tx_frame_len; wire [15:0] rx_frame_len; - wire [7:0] rate; wire bus_error; wire clear_tx, clear_rx; @@ -111,6 +112,8 @@ module u1e_core .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), + + .test_rate(test_rate), .test_ctrl(test_ctrl), .debug(debug_gpmc)); wire rx_sof = rx_data[32]; @@ -285,9 +288,8 @@ module u1e_core xfer_rate <= s0_dat_mosi; endcase // case (s0_adr[6:0]) - assign tx_enable = xfer_rate[15]; - assign rx_enable = xfer_rate[14]; - assign rate = xfer_rate[7:0]; + assign test_ctrl = xfer_rate[11:8]; + assign test_rate = xfer_rate[7:0]; assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]}; assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; -- cgit v1.2.3 From 87f8f6fca6742a4263b636aa5632f228fccd18f2 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 25 Feb 2011 13:46:03 -0500 Subject: timed tester : Bring out src/dst flags for rx chain for testing. --- usrp2/gpmc/gpmc_async.v | 12 +++++++++++- usrp2/top/u1e/u1e_core.v | 4 ++++ 2 files changed, 15 insertions(+), 1 deletion(-) (limited to 'usrp2') diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 7d38c66cb..053df5b18 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -129,7 +129,7 @@ module gpmc_async .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i) ); - assign debug = pkt_count; +// assign debug = pkt_count; // //////////////////////////////////////////// // Test support, traffic generator, loopback, etc. @@ -213,4 +213,14 @@ module gpmc_async // FIXME -- make sure packet completes before we shutoff // FIXME -- handle overrun and underrun +wire [0:17] dummy18; + +assign debug = {dummy18, timedrx_src_rdy_int, timedrx_dst_rdy_int, + timedrx_src_rdy, timedrx_dst_rdy, + testrx_src_rdy, testrx_dst_rdy, + rx_src_rdy, rx_dst_rdy, + rx36_src_rdy, rx36_dst_rdy, + rx18_src_rdy, rx18_dst_rdy, + rx18b_src_rdy, rx18b_dst_rdy}; + endmodule // gpmc_async diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 174a2a3f8..a5a477202 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -408,10 +408,14 @@ module u1e_core assign debug_clk = { EM_CLK, clk_fpga }; +/* assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun }, { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, { EM_D } }; +*/ + assign debug = debug_gpmc; + assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; -- cgit v1.2.3 From 98a1a03de054306f57be68e1b498c1d39a954472 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 25 Feb 2011 15:17:31 -0800 Subject: fifo36_mux now has shortfifos on the input ports as well as output --- usrp2/fifo/fifo36_mux.v | 37 +++++++++++++++++++++++++------------ usrp2/gpmc/fifo_to_gpmc_async.v | 5 ----- usrp2/gpmc/gpmc_async.v | 4 +++- 3 files changed, 28 insertions(+), 18 deletions(-) (limited to 'usrp2') diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index c6fd40f27..fa4243efe 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -10,6 +10,19 @@ module fifo36_mux input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + wire [35:0] data0_int, data1_int; + wire src0_rdy_int, dst0_rdy_int, src1_rdy_int, dst1_rdy_int; + + fifo_short #(.WIDTH(36)) mux_fifo_in0 + (.clk(clk), .reset(reset), .clear(clear), + .datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_i), + .dataout(data0_int), .src_rdy_o(src0_rdy_int), .dst_rdy_i(dst0_rdy_int)); + + fifo_short #(.WIDTH(36)) mux_fifo_in1 + (.clk(clk), .reset(reset), .clear(clear), + .datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_i), + .dataout(data1_int), .src_rdy_o(src1_rdy_int), .dst_rdy_i(dst1_rdy_int)); + localparam MUX_IDLE0 = 0; localparam MUX_DATA0 = 1; localparam MUX_IDLE1 = 2; @@ -17,8 +30,8 @@ module fifo36_mux reg [1:0] state; - wire eof0 = data0_i[33]; - wire eof1 = data1_i[33]; + wire eof0 = data0_int[33]; + wire eof1 = data1_int[33]; wire [35:0] data_int; wire src_rdy_int, dst_rdy_int; @@ -29,33 +42,33 @@ module fifo36_mux else case(state) MUX_IDLE0 : - if(src0_rdy_i) + if(src0_rdy_int) state <= MUX_DATA0; - else if(src1_rdy_i) + else if(src1_rdy_int) state <= MUX_DATA1; MUX_DATA0 : - if(src0_rdy_i & dst_rdy_int & eof0) + if(src0_rdy_int & dst_rdy_int & eof0) state <= prio ? MUX_IDLE0 : MUX_IDLE1; MUX_IDLE1 : - if(src1_rdy_i) + if(src1_rdy_int) state <= MUX_DATA1; - else if(src0_rdy_i) + else if(src0_rdy_int) state <= MUX_DATA0; MUX_DATA1 : - if(src1_rdy_i & dst_rdy_int & eof1) + if(src1_rdy_int & dst_rdy_int & eof1) state <= MUX_IDLE0; default : state <= MUX_IDLE0; endcase // case (state) - assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_int : 0; - assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_int : 0; - assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; - assign data_int = (state==MUX_DATA0) ? data0_i : data1_i; + assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0; + assign dst1_rdy_int = (state==MUX_DATA1) ? dst_rdy_int : 0; + assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0; + assign data_int = (state==MUX_DATA0) ? data0_int : data1_int; fifo_short #(.WIDTH(36)) mux_fifo (.clk(clk), .reset(reset), .clear(clear), diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v index cf8b6e861..9a8e37ce9 100644 --- a/usrp2/gpmc/fifo_to_gpmc_async.v +++ b/usrp2/gpmc/fifo_to_gpmc_async.v @@ -1,9 +1,4 @@ -// Assumes an asynchronous GPMC cycle -// If a packet bigger or smaller than we are told is sent, behavior is undefined. -// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. -// If there is a bus error, we should be reset - module fifo_to_gpmc_async (input clk, input reset, input clear, input [17:0] data_i, input src_rdy_i, output dst_rdy_o, diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 053df5b18..02bf45b8a 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -215,7 +215,9 @@ module gpmc_async wire [0:17] dummy18; -assign debug = {dummy18, timedrx_src_rdy_int, timedrx_dst_rdy_int, +assign debug = {8'd0, + test_rate, + pkt_src_enable, pkt_sink_enable, timedrx_src_rdy_int, timedrx_dst_rdy_int, timedrx_src_rdy, timedrx_dst_rdy, testrx_src_rdy, testrx_dst_rdy, rx_src_rdy, rx_dst_rdy, -- cgit v1.2.3 From 8b541ef9af7e10e072758c5ad75454fd4dcdf709 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 25 Feb 2011 16:44:50 -0800 Subject: correct port names --- usrp2/fifo/fifo36_mux.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'usrp2') diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index fa4243efe..7f0f803ff 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -15,12 +15,12 @@ module fifo36_mux fifo_short #(.WIDTH(36)) mux_fifo_in0 (.clk(clk), .reset(reset), .clear(clear), - .datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_i), + .datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_o), .dataout(data0_int), .src_rdy_o(src0_rdy_int), .dst_rdy_i(dst0_rdy_int)); fifo_short #(.WIDTH(36)) mux_fifo_in1 (.clk(clk), .reset(reset), .clear(clear), - .datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_i), + .datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_o), .dataout(data1_int), .src_rdy_o(src1_rdy_int), .dst_rdy_i(dst1_rdy_int)); localparam MUX_IDLE0 = 0; -- cgit v1.2.3 From 8d82fcacc459caac6b3d4ddfd3821f69cc9037ea Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sat, 26 Feb 2011 17:30:46 -0500 Subject: timed packet generator : Temporarily use a checksum rather than a crc to validate packet integrity. --- usrp2/fifo/packet_generator.v | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'usrp2') diff --git a/usrp2/fifo/packet_generator.v b/usrp2/fifo/packet_generator.v index bbcab6db2..2ae911e24 100644 --- a/usrp2/fifo/packet_generator.v +++ b/usrp2/fifo/packet_generator.v @@ -10,7 +10,7 @@ module packet_generator reg [31:0] state; reg [31:0] seq; - wire [31:0] crc_out; + reg [31:0] crc_out; wire calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF); @@ -71,7 +71,13 @@ module packet_generator wire clear_crc = eof_o & src_rdy_o & dst_rdy_i; - crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), - .calc(calc_crc), .crc_out(crc_out), .match()); +// crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), +// .calc(calc_crc), .crc_out(crc_out), .match()); + always @(posedge clk) + if(reset | clear | clear_crc) + crc_out <= 0; + else + if(calc_crc) + crc_out <= crc_out + data_o; endmodule // packet_generator -- cgit v1.2.3