From d8a044097cb68f4bb9ed2727799568d534f631de Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Fri, 26 Aug 2011 13:27:19 -0700
Subject: fpga: minor tweaks to build system
---
usrp2/top/Makefile.common | 1 -
usrp2/top/python/check_timing.py | 5 ++++-
2 files changed, 4 insertions(+), 2 deletions(-)
(limited to 'usrp2')
diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common
index 3a35e71e7..3b71e7b13 100644
--- a/usrp2/top/Makefile.common
+++ b/usrp2/top/Makefile.common
@@ -36,7 +36,6 @@ synth: $(ISE_FILE)
$(ISE_HELPER) "Synthesize - XST"
bin: check $(BIN_FILE)
- $(ISE_HELPER) "Generate Programming File"
$(TIMING_CHECKER) $(TWR_FILE)
mcs: $(MCS_FILE)
diff --git a/usrp2/top/python/check_timing.py b/usrp2/top/python/check_timing.py
index c57e889d0..0c5918096 100755
--- a/usrp2/top/python/check_timing.py
+++ b/usrp2/top/python/check_timing.py
@@ -21,10 +21,13 @@ import re
def print_timing_constraint_summary(twr_file):
output = ""
keep = False
+ done = False
for line in open(twr_file).readlines():
if 'Derived Constraint Report' in line: keep = True
+ if 'constraint' in line and 'met' in line: done = True
+ if not keep and done: keep = True
if keep: output += line
- if 'constraint' in line and 'met' in line: break
+ if done: break
print("\n\n"+output)
if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:])
--
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