From bcb80c5cf9a2117f9d6d22b8e793ea2ecb68ed1f Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Sat, 5 Nov 2011 18:12:32 -0700
Subject: remove unused irq to meet timing
---
usrp2/top/N2x0/u2plus_core.v | 13 +++----------
usrp2/top/USRP2/u2_core.v | 15 ++++-----------
2 files changed, 7 insertions(+), 21 deletions(-)
(limited to 'usrp2')
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index 861b3833f..dd3d33b37 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -444,7 +444,7 @@ module u2plus_core
.word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
.word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
.word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
- .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),
+ .word11(vita_time[31:0]),.word12(compat_num),.word13({18'b0, button, 13'b0}),
.word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
);
@@ -523,17 +523,10 @@ module u2plus_core
// /////////////////////////////////////////////////////////////////////////
// Interrupt Controller, Slave #8
- // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic
- wire underrun_wb, overrun_wb, pps_wb;
-
- oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb));
- oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun0 | overrun1), .clk_out(wb_clk), .out(overrun_wb));
- oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb));
-
assign irq= {{8'b0},
{uart_tx_int[3:0], uart_rx_int[3:0]},
- {2'b0, button, periodic_int, clk_status, serdes_link_up, 2'b00},
- {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}};
+ {4'b0, clk_status, 3'b0},
+ {3'b0, PHY_INTn,i2c_int,spi_int,2'b00}};
pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]),
.we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index b4e17aa67..d3524c304 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -450,7 +450,7 @@ module u2_core
.word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
.word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
.word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
- .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),
+ .word11(vita_time[31:0]),.word12(compat_num),.word13(32'b0),
.word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
);
@@ -526,17 +526,10 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// Interrupt Controller, Slave #8
- // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic
- wire underrun_wb, overrun_wb, pps_wb;
-
- oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb));
- oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun0 | overrun1), .clk_out(wb_clk), .out(overrun_wb));
- oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb));
-
assign irq= {{8'b0},
- {8'b0},
- {2'b0, good_sync, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
- {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}};
+ {3'b0, uart_tx_int, 2'b0, uart_rx_int},
+ {4'b0, clk_status, 3'b0},
+ {3'b0, PHY_INTn,i2c_int,spi_int,2'b00}};
pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]),
.we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
--
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