From b7e1b9ce77a0df46a5b336fda1e1972aa8199488 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 7 Jun 2010 14:22:30 -0700
Subject: compiles now, added clock constraints

---
 usrp2/top/u2plus/Makefile   | 28 +++++++++++++++++++++++++---
 usrp2/top/u2plus/u2plus.ucf | 18 ++++++++++++++++++
 2 files changed, 43 insertions(+), 3 deletions(-)

(limited to 'usrp2')

diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile
index 305b5b9e3..29928e03e 100644
--- a/usrp2/top/u2plus/Makefile
+++ b/usrp2/top/u2plus/Makefile
@@ -70,6 +70,7 @@ control_lib/ram_harv_cache.v \
 control_lib/ram_loader.v \
 control_lib/setting_reg.v \
 control_lib/settings_bus.v \
+control_lib/settings_bus_crossclock.v \
 control_lib/srl.v \
 control_lib/system_control.v \
 control_lib/wb_1master.v \
@@ -82,7 +83,18 @@ control_lib/sd_spi.v \
 control_lib/sd_spi_wb.v \
 control_lib/wb_bridge_16_32.v \
 control_lib/reset_sync.v \
+control_lib/priority_enc.v \
+control_lib/pic.v \
+vrt/vita_rx_control.v \
+vrt/vita_rx_framer.v \
+vrt/vita_tx_control.v \
+vrt/vita_tx_deframer.v \
+udp/udp_wrapper.v \
+udp/fifo19_rxrealign.v \
+udp/prot_eng_tx.v \
+udp/add_onescomp.v \
 simple_gemac/simple_gemac_wrapper.v \
+simple_gemac/simple_gemac_wrapper19.v \
 simple_gemac/simple_gemac.v \
 simple_gemac/simple_gemac_wb.v \
 simple_gemac/simple_gemac_tx.v \
@@ -103,11 +115,15 @@ control_lib/newfifo/buffer_pool.v \
 control_lib/newfifo/fifo_2clock.v \
 control_lib/newfifo/fifo_2clock_cascade.v \
 control_lib/newfifo/ll8_shortfifo.v \
-control_lib/newfifo/ll8_to_fifo36.v \
 control_lib/newfifo/fifo_short.v \
 control_lib/newfifo/fifo_long.v \
 control_lib/newfifo/fifo_cascade.v \
 control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+control_lib/newfifo/fifo19_to_ll8.v \
+control_lib/newfifo/ll8_to_fifo19.v \
+control_lib/newfifo/fifo36_to_fifo19.v \
+control_lib/newfifo/fifo19_to_fifo36.v \
 control_lib/longfifo.v \
 control_lib/shortfifo.v \
 control_lib/medfifo.v \
@@ -117,6 +133,10 @@ coregen/fifo_xlnx_512x36_2clk.v \
 coregen/fifo_xlnx_512x36_2clk.xco \
 coregen/fifo_xlnx_64x36_2clk.v \
 coregen/fifo_xlnx_64x36_2clk.xco \
+coregen/fifo_xlnx_16x19_2clk.v \
+coregen/fifo_xlnx_16x19_2clk.xco \
+coregen/fifo_xlnx_16x40_2clk.v \
+coregen/fifo_xlnx_16x40_2clk.xco \
 extram/wb_zbt16_b.v \
 opencores/8b10b/decode_8b10b.v \
 opencores/8b10b/encode_8b10b.v \
@@ -132,7 +152,6 @@ opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
 opencores/i2c/rtl/verilog/i2c_master_defines.v \
 opencores/i2c/rtl/verilog/i2c_master_top.v \
 opencores/i2c/rtl/verilog/timescale.v \
-opencores/simple_pic/rtl/simple_pic.v \
 opencores/spi/rtl/verilog/spi_clgen.v \
 opencores/spi/rtl/verilog/spi_defines.v \
 opencores/spi/rtl/verilog/spi_shift.v \
@@ -170,10 +189,13 @@ serdes/serdes_fc_rx.v \
 serdes/serdes_fc_tx.v \
 serdes/serdes_rx.v \
 serdes/serdes_tx.v \
+timing/time_64bit.v \
+timing/time_compare.v \
 timing/time_receiver.v \
 timing/time_sender.v \
 timing/time_sync.v \
 timing/timer.v \
+timing/simple_timer.v \
 top/u2_core/u2_core.v \
 top/u2plus/capture_ddrlvds.v \
 top/u2plus/u2plus.ucf \
@@ -183,7 +205,7 @@ top/u2plus/u2plus.v
 # Process Properties
 ##################################################
 export SYNTHESIZE_PROPERTIES := \
-"Number of Clock Buffers" 6 \
+"Number of Clock Buffers" 8 \
 "Pack I/O Registers into IOBs" Yes \
 "Optimization Effort" High \
 "Optimize Instantiated Primitives" TRUE \
diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf
index 31404dda9..a3cd61906 100755
--- a/usrp2/top/u2plus/u2plus.ucf
+++ b/usrp2/top/u2plus/u2plus.ucf
@@ -399,3 +399,21 @@ NET "flash_cs"  LOC = "AA7"  ;
 #NET "unnamed_net11"  LOC = "G7"  ;     # TDI
 #NET "unnamed_net10"  LOC = "A25"  ;    # TCK
 #NET "unnamed_net20"  LOC = "V20"  ;    # SUSPEND
+
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
+
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
+TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns;
-- 
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