From a0dfafffbf64ba007fc8695e105c72c93c654319 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 10 Nov 2010 11:50:42 -0800 Subject: need to enable both 16 and 32 bit spi interfaces -- 16 used in u1e, 32 in u2 and u2p --- usrp2/opencores/Makefile.srcs | 1 + 1 file changed, 1 insertion(+) (limited to 'usrp2') diff --git a/usrp2/opencores/Makefile.srcs b/usrp2/opencores/Makefile.srcs index 1ccecf337..284578b39 100644 --- a/usrp2/opencores/Makefile.srcs +++ b/usrp2/opencores/Makefile.srcs @@ -23,5 +23,6 @@ i2c/rtl/verilog/timescale.v \ spi/rtl/verilog/spi_clgen.v \ spi/rtl/verilog/spi_defines.v \ spi/rtl/verilog/spi_shift.v \ +spi/rtl/verilog/spi_top.v \ spi/rtl/verilog/spi_top16.v \ )) -- cgit v1.2.3